soc/rockchip/rk3399/clock: Add rkclk_ddr_reset() function
This adds the rkclk_ddr_reset() function equivalent for the RK3399.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: If1da85064d75bdf49b7555d09257409443c25e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50889
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 0ba07d6..182e398 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -650,6 +650,16 @@
rkclk_set_dpllssc(&dpll_cfg);
}
+#define CRU_SFTRST_DDR_CTRL(ch, n) ((1 << 16 | (n)) << (8 + (ch) * 4))
+#define CRU_SFTRST_DDR_PHY(ch, n) ((1 << 16 | (n)) << (9 + (ch) * 4))
+
+void rkclk_ddr_reset(u32 channel, u32 ctl, u32 phy)
+{
+ write32(&cru_ptr->softrst_con[4],
+ CRU_SFTRST_DDR_CTRL(channel, ctl) |
+ CRU_SFTRST_DDR_PHY(channel, phy));
+}
+
#define SPI_CLK_REG_VALUE(bus, clk_div) \
RK_CLRSETBITS(CLK_SPI_PLL_SEL_MASK << \
CLK_SPI ##bus## _PLL_SEL_SHIFT | \