diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index ba37610..ec036c9 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -23,6 +23,7 @@
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
+#include <stage_cache.h>
 #include <cpu/intel/smm/gen1/smi.h>
 #include "nehalem.h"
 
@@ -38,11 +39,25 @@
 	return (u32)smm_region_start();
 }
 
+u32 northbridge_get_tseg_size(void)
+{
+	return CONFIG_SMM_TSEG_SIZE;
+}
+
 void *cbmem_top(void)
 {
 	return (void *) smm_region_start();
 }
 
+void stage_cache_external_region(void **base, size_t *size)
+{
+	/* The stage cache lives at the end of TSEG region.
+	 * The top of RAM is defined to be the TSEG base address. */
+	*size = CONFIG_SMM_RESERVED_SIZE;
+	*base = (void *)((uintptr_t)northbridge_get_tseg_base() +
+			northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+}
+
 /* platform_enter_postcar() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use,
  * and continues execution in postcar stage. */