intel/nehalem,sandybridge: Move stage_cache support function
Let garbage-collection take care of stage_cache_external_region()
if it is no needed and move implementation to a suitable file already
building for needed stages.
Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE and
(unused) aliasing of CONFIG_IED_REGION_SIZE as IED_SIZE.
Change-Id: Idf00ba3180d8c3bc974dd3c5ca5f98a6c08bf34d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34672
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index b220c2d..93024f6 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -122,9 +122,6 @@
#define IVB_STEP_K0 (BASE_REV_IVB + 5)
#define IVB_STEP_D0 (BASE_REV_IVB + 6)
-/* Intel Enhanced Debug region must be 4MB */
-#define IED_SIZE 0x400000
-
/* Northbridge BARs */
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 485cb27..a058d3f 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -171,11 +171,6 @@
add_fixed_resources(dev, 10);
}
-u32 northbridge_get_tseg_size(void)
-{
- return CONFIG_SMM_TSEG_SIZE;
-}
-
static void mc_set_resources(struct device *dev)
{
/* And call the normal set_resources */
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index ba37610..ec036c9 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -23,6 +23,7 @@
#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
#include <program_loading.h>
+#include <stage_cache.h>
#include <cpu/intel/smm/gen1/smi.h>
#include "nehalem.h"
@@ -38,11 +39,25 @@
return (u32)smm_region_start();
}
+u32 northbridge_get_tseg_size(void)
+{
+ return CONFIG_SMM_TSEG_SIZE;
+}
+
void *cbmem_top(void)
{
return (void *) smm_region_start();
}
+void stage_cache_external_region(void **base, size_t *size)
+{
+ /* The stage cache lives at the end of TSEG region.
+ * The top of RAM is defined to be the TSEG base address. */
+ *size = CONFIG_SMM_RESERVED_SIZE;
+ *base = (void *)((uintptr_t)northbridge_get_tseg_base() +
+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+}
+
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 5aa06c8..233384c 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -444,28 +444,6 @@
MCHBAR32(0x5500) = 0x00100001;
}
-static u32 northbridge_get_base_reg(struct device *dev, int reg)
-{
- u32 value;
-
- value = pci_read_config32(dev, reg);
- /* Base registers are at 1MiB granularity. */
- value &= ~((1 << 20) - 1);
- return value;
-}
-
-u32 northbridge_get_tseg_base(void)
-{
- struct device *dev = pcidev_on_root(0, 0);
-
- return northbridge_get_base_reg(dev, TSEG);
-}
-
-u32 northbridge_get_tseg_size(void)
-{
- return CONFIG_SMM_TSEG_SIZE;
-}
-
void northbridge_write_smram(u8 smram)
{
pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram);
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
index 343ae62..7d5c173 100644
--- a/src/northbridge/intel/sandybridge/ram_calc.c
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -20,17 +20,12 @@
#include <cbmem.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
+#include <cpu/intel/smm/gen1/smi.h>
#include <cpu/x86/mtrr.h>
#include <program_loading.h>
+#include <stage_cache.h>
#include "sandybridge.h"
-#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
-# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
-#endif
-#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
-# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
-#endif
-
static uintptr_t smm_region_start(void)
{
/* Base of TSEG is top of usable DRAM */
@@ -43,6 +38,25 @@
return (void *) smm_region_start();
}
+u32 northbridge_get_tseg_base(void)
+{
+ return ALIGN_DOWN(smm_region_start(), 1*MiB);
+}
+
+u32 northbridge_get_tseg_size(void)
+{
+ return CONFIG_SMM_TSEG_SIZE;
+}
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+ /* The stage cache lives at the end of TSEG region.
+ * The top of RAM is defined to be the TSEG base address. */
+ *size = CONFIG_SMM_RESERVED_SIZE;
+ *base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size()
+ - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE);
+}
+
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 88b7b56..b488f2c 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -34,10 +34,6 @@
#define IVB_STEP_K0 (BASE_REV_IVB + 5)
#define IVB_STEP_D0 (BASE_REV_IVB + 6)
-/* Intel Enhanced Debug region must be 4MB */
-
-#define IED_SIZE CONFIG_IED_REGION_SIZE
-
/* Northbridge BARs */
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */