soc/amd/picasso/fch: use [read,write]8p to avoid typecasts
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8445f209e43366b43b9c4750bc5f074f6d4144aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67978
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c
index c4d34a53..b83e700 100644
--- a/src/soc/amd/picasso/fch.c
+++ b/src/soc/amd/picasso/fch.c
@@ -165,12 +165,12 @@
uint8_t al2ahb_val;
uintptr_t al2ahb_base = ALINK_AHB_ADDRESS;
- al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET));
+ al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET);
al2ahb_val |= AL2AHB_CLK_GATE_EN;
- write8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET), al2ahb_val);
- al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET));
+ write8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET, al2ahb_val);
+ al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET);
al2ahb_val |= AL2AHB_HCLK_GATE_EN;
- write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val);
+ write8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET, al2ahb_val);
}
/* configure the general purpose PCIe clock outputs according to the devicetree settings */