commit f672f7ff7d6e1fd607c4348ac45132a1e3064585
author Subrata Banik <subrata.banik@intel.com> Mon Aug 03 14:29:25 2020 +0530
committer Subrata Banik <subrata.banik@intel.com> Wed Aug 05 05:38:14 2020 +0000
tree ca4fe63e55f1885e63a6ccac4425def60e2d55c5
parent d1c590a66654bdb6be6da85c539c9567be6234a0

soc/intel/common: Include Alder Lake device IDs

Add Alder Lake specific CPU, System Agent, PCH (Alder Point aka ADP),
IGD device IDs.

Document Number: 619501, 619362

Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/common/block/spi/spi.c

diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
index cd5c4d4..295df09 100644
--- a/src/soc/intel/common/block/spi/spi.c
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -87,6 +87,22 @@
 	PCI_DEVICE_ID_INTEL_JSP_SPI1,
 	PCI_DEVICE_ID_INTEL_JSP_SPI2,
 	PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI,
+	PCI_DEVICE_ID_INTEL_ADP_P_HWSEQ_SPI,
+	PCI_DEVICE_ID_INTEL_ADP_S_HWSEQ_SPI,
+	PCI_DEVICE_ID_INTEL_ADP_P_SPI0,
+	PCI_DEVICE_ID_INTEL_ADP_P_SPI1,
+	PCI_DEVICE_ID_INTEL_ADP_P_SPI2,
+	PCI_DEVICE_ID_INTEL_ADP_P_SPI3,
+	PCI_DEVICE_ID_INTEL_ADP_P_SPI4,
+	PCI_DEVICE_ID_INTEL_ADP_P_SPI5,
+	PCI_DEVICE_ID_INTEL_ADP_P_SPI6,
+	PCI_DEVICE_ID_INTEL_ADP_S_SPI0,
+	PCI_DEVICE_ID_INTEL_ADP_S_SPI1,
+	PCI_DEVICE_ID_INTEL_ADP_S_SPI2,
+	PCI_DEVICE_ID_INTEL_ADP_S_SPI3,
+	PCI_DEVICE_ID_INTEL_ADP_S_SPI4,
+	PCI_DEVICE_ID_INTEL_ADP_S_SPI5,
+	PCI_DEVICE_ID_INTEL_ADP_S_SPI6,
 	0
 };