Move calls to quick_ram_check() before CBMEM init
After raminit completes, do a read-modify-write test
just below CBMEM top address. If test fails, die().
Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index ee87eff..0426bb4 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -20,7 +20,6 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
-#include <lib.h>
#include <timestamp.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
@@ -121,9 +120,6 @@
intel_early_me_status();
- quick_ram_check();
- post_code(0x3e);
-
if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */
diff --git a/src/include/lib.h b/src/include/lib.h
index 3edc372..098d62d 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -24,10 +24,11 @@
size_t ulzman(const void *src, size_t srcn, void *dst, size_t dstn);
/* Defined in src/lib/ramtest.c */
+/* Assumption is 32-bit addressable UC memory. */
void ram_check(unsigned long start, unsigned long stop);
int ram_check_nodie(unsigned long start, unsigned long stop);
int ram_check_noprint_nodie(unsigned long start, unsigned long stop);
-void quick_ram_check(void);
+void quick_ram_check_or_die(uintptr_t dst);
/* Defined in primitive_memtest.c */
int primitive_memtest(uintptr_t base, uintptr_t size);
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index c458e5e..1a67ad5 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <cbmem.h>
#include <imd.h>
+#include <lib.h>
#include <stdlib.h>
#include <arch/early_variables.h>
@@ -119,6 +120,10 @@
return;
cbmem_top_init();
+
+ /* The test is only effective on X86 and when address hits UC memory. */
+ if (ENV_X86)
+ quick_ram_check_or_die((uintptr_t)cbmem_top() - sizeof(u32));
}
void cbmem_initialize_empty_id_size(u32 id, u64 size)
diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c
index eb58c30..489ca28 100644
--- a/src/lib/ramtest.c
+++ b/src/lib/ramtest.c
@@ -171,7 +171,10 @@
return failures;
}
-static void __quick_ram_check(uintptr_t dst)
+/* Assumption is 32-bit addressable UC memory at dst. This also executes
+ * on S3 resume path so target memory must be restored.
+ */
+void quick_ram_check_or_die(uintptr_t dst)
{
int fail = 0;
u32 backup;
@@ -200,8 +203,3 @@
}
phys_memory_barrier();
}
-
-void quick_ram_check(void)
-{
- __quick_ram_check(0x100000);
-}
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index c5a3120..7e895b4 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -23,7 +23,6 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
-#include <lib.h>
#include <romstage_handoff.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
@@ -273,7 +272,4 @@
}
romstage_handoff_init(s3resume);
-
- if (!s3resume)
- quick_ram_check();
}
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index b20c445..35b90f6 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -23,7 +23,6 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
-#include <lib.h>
#include <romstage_handoff.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
@@ -266,7 +265,4 @@
}
romstage_handoff_init(s3resume);
-
- if (!s3resume)
- quick_ram_check();
}
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index cf1da63..e6a344e 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -18,7 +18,6 @@
*/
#include <arch/io.h>
-#include <lib.h>
#include <timestamp.h>
#include <console/console.h>
#include <device/pci_ops.h>
@@ -105,8 +104,6 @@
post_code(0x31);
- quick_ram_check();
-
mb_pirq_setup();
rcba_config();
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 3f62d10..4a048db 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -31,7 +31,6 @@
#include <southbridge/intel/common/smbus.h>
#include <cpu/x86/msr.h>
#include <delay.h>
-#include <lib.h>
#include "raminit_native.h"
#include "raminit_common.h"
#include "sandybridge.h"
@@ -419,9 +418,6 @@
/* Zone config */
dram_zones(&ctrl, 0);
- /* Non intrusive, fast ram check */
- quick_ram_check();
-
intel_early_me_status();
intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
intel_early_me_status();
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 72ef1a9..02a8b74 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -23,7 +23,6 @@
#include <arch/cpu.h>
#include <delay.h>
#include <halt.h>
-#include <lib.h>
#include "iomap.h"
#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
@@ -734,6 +733,5 @@
}
timestamp_add_now(TS_AFTER_INITRAM);
- quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");
}
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 04657ae..8d43907 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -20,7 +20,6 @@
#include <cf9_reset.h>
#include <console/console.h>
#include <device/pci_def.h>
-#include <lib.h>
#include <memory_info.h>
#include <mrc_cache.h>
#include <string.h>
@@ -98,9 +97,6 @@
report_memory_config();
- /* Basic memory sanity test */
- quick_ram_check();
-
if (pei_data->boot_mode != ACPI_S3) {
cbmem_initialize_empty();
} else if (cbmem_initialize()) {
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index b4eb006..c46b09e 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -15,7 +15,6 @@
*/
#include <stddef.h>
-#include <lib.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
@@ -245,12 +244,6 @@
late_mainboard_romstage_entry();
post_code(0x4c);
- /* if S3 resume skip RAM check */
- if (prev_sleep_state != ACPI_S3) {
- quick_ram_check();
- post_code(0x4d);
- }
-
cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3);
/* Save the HOB pointer in CBMEM to be used in ramstage*/
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 36e9e6b..a75dabd 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -16,7 +16,6 @@
*/
#include <stddef.h>
-#include <lib.h>
#include <device/pci_ops.h>
#include <arch/cbfs.h>
#include <cbmem.h>
@@ -112,9 +111,6 @@
post_code(0x4b);
late_mainboard_romstage_entry();
- post_code(0x4c);
- quick_ram_check();
-
post_code(0x4d);
cbmem_was_initted = !cbmem_recovery(0);
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 14611b3..19e470e 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <lib.h>
#include <timestamp.h>
#include <arch/io.h>
#include <device/mmio.h>
@@ -114,9 +113,6 @@
/* Decode E0000 and F0000 segment to DRAM */
sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0));
- quick_ram_check();
- post_code(0x4d);
-
cbmem_was_initted = !cbmem_recovery(0);
/* Save the HOB pointer in CBMEM to be used in ramstage*/