mb/google/myst: Re-organize the FMAP layout
By moving certain FW UI assets from RO to RW sections, 4 MiB is
sufficient for RO section. Split the resultant available 4 MiB equally
between 2 RW sections. This will help in getting to 16 MiB SPI flash for
the mainboard.
BUG=b:281567816
TEST=Build Myst BIOS image with the updated layout.
Cq-Depend: chromium:4519688
Change-Id: I09948ceac0a6a1cb109322fc4856b8b486318664
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75184
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
diff --git a/src/mainboard/google/myst/chromeos.fmd b/src/mainboard/google/myst/chromeos.fmd
index 56a163d..e1502e1 100644
--- a/src/mainboard/google/myst/chromeos.fmd
+++ b/src/mainboard/google/myst/chromeos.fmd
@@ -1,7 +1,7 @@
# TODO(b/276944900): Update for 32 MB support, evaluate WP_RO size
FLASH@0xFF000000 16M {
SI_BIOS {
- WP_RO 8M {
+ WP_RO 4M {
RO_GSCVD 8K
RO_VPD(PRESERVE) 16K
RO_SECTION {
@@ -11,16 +11,16 @@
GBB 12K
}
}
- RW_SECTION_A 3M {
+ RW_SECTION_A 5M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
- SIGNED_AMDFW_A 1536K
+ SIGNED_AMDFW_A 2304K
RW_FWID_A 256
}
- RW_SECTION_B 3M {
+ RW_SECTION_B 5M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
- SIGNED_AMDFW_B 1536K
+ SIGNED_AMDFW_B 2304K
RW_FWID_B 256
}
RW_ELOG(PRESERVE) 4K