tree b54c13b170bc73bfc99dbd46724254bbe00c1de8
parent 9cd1bf2c17932e5985c5156dfa5fea76c25da725
author Angel Pons <th3fanbus@gmail.com> 1631100617 +0200
committer Lean Sheng Tan <sheng.tan@9elements.com> 1713128056 +0000

lynxpoint/broadwell: Correct PCH-LP PCIe ASPM check

Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM
on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also
uses bit 29 for root port #6. Correct the bit used in the check, as well
as the surrounding comments.

Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>