soc/intel: Drop casts around `soc_read_pmc_base()`
The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then
casted to a pointer type for use with `read32()` and/or `write32()`. But
since commit b324df6a540d154cc9267c0398654f9142aae052 (arch/x86: Provide
readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()`
functions live in `arch/mmio.h`. These functions use the `uintptr_t type
for the address parameter instead of a pointer type, and using them with
the `soc_read_pmc_base()` function allows dropping the casts to pointer.
Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index d3a21a1..a5f2dca 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -368,8 +368,8 @@
/* Read PMC base address from soc */
pmc_bar = soc_read_pmc_base();
- prsts = read32((void *)(pmc_bar + PRSTS));
- write32((void *)(pmc_bar + PRSTS), prsts);
+ prsts = read32p(pmc_bar + PRSTS);
+ write32p(pmc_bar + PRSTS, prsts);
soc_clear_pm_registers(pmc_bar);
}
@@ -559,7 +559,7 @@
*/
if (dw0 == dw1 || dw1 == dw2) {
printk(BIOS_INFO, "PMC: Using default GPE route.\n");
- gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG);
+ gpio_cfg = read32p(pmc_bar + GPIO_GPE_CFG);
dw0 = (gpio_cfg >> GPE0_DW_SHIFT(0)) & GPE0_DWX_MASK;
dw1 = (gpio_cfg >> GPE0_DW_SHIFT(1)) & GPE0_DWX_MASK;
@@ -570,10 +570,10 @@
gpio_cfg |= (uint32_t) dw2 << GPE0_DW_SHIFT(2);
}
- gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;
+ gpio_cfg_reg = read32p(pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;
gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
- write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg);
+ write32p(pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg);
/* Set the routes in the GPIO communities as well. */
gpio_route_gpe(dw0, dw1, dw2);