sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different
filenames from common code.
Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c
index f69cb93..671bfc5 100644
--- a/src/southbridge/intel/i82371eb/early_smbus.c
+++ b/src/southbridge/intel/i82371eb/early_smbus.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <console/console.h>
#include <device/pci_ops.h>
#include <device/pci.h>
#include <device/pci_ids.h>
@@ -29,7 +28,12 @@
enable_pm();
}
-void enable_smbus(void)
+uintptr_t smbus_base(void)
+{
+ return SMBUS_IO_BASE;
+}
+
+int smbus_enable_iobar(uintptr_t base)
{
pci_devfn_t dev;
u8 reg8;
@@ -40,7 +44,7 @@
PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
/* Set the SMBus I/O base. */
- pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
+ pci_write_config32(dev, SMBBA, base | 1);
/* Enable the SMBus controller host interface. */
reg8 = pci_read_config8(dev, SMBHSTCFG);
@@ -52,9 +56,7 @@
reg16 |= PCI_COMMAND_IO;
pci_write_config16(dev, PCI_COMMAND, reg16);
- smbus_host_reset(SMBUS_IO_BASE);
-
- printk(BIOS_DEBUG, "SMBus controller enabled\n");
+ return 0;
}
int smbus_read_byte(u8 device, u8 address)