diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 2c16818..b45c442 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1711,7 +1711,7 @@
 					.rank    = slotrank,
 				},
 			},
-			/* DRAM command RD */
+			/* DRAM command RDA */
 			[2] = {
 				.sp_cmd_ctrl = {
 					.command    = IOSAV_RD,
diff --git a/src/northbridge/intel/sandybridge/registers/mchbar.h b/src/northbridge/intel/sandybridge/registers/mchbar.h
index d3df3c0..bdf85dc 100644
--- a/src/northbridge/intel/sandybridge/registers/mchbar.h
+++ b/src/northbridge/intel/sandybridge/registers/mchbar.h
@@ -112,7 +112,7 @@
  *          end architecture RTL;
  *
  *   [16]       Chip Select mode control.
- *   [17]       Auto Precharge. Only valid when using 10 row bits!
+ *   [17]       Auto Precharge. Used to send RDA commands.
  *
  * IOSAV_n_SUBSEQ_CTRL_ch(channel, index)
  *   The parameters of the subseq: number of repetitions of the command,