diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index e6464aa..a57f976 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -62,7 +62,7 @@
 	}
 }
 
-void fsp_silicon_init(bool s3wake)
+void fsps_load(bool s3wake)
 {
 	struct fsp_header *hdr = &fsps_hdr;
 	struct cbfsf file_desc;
@@ -71,17 +71,20 @@
 	void *dest;
 	size_t size;
 	struct prog fsps = PROG_INIT(PROG_REFCODE, name);
+	static int load_done;
+
+	if (load_done)
+		return;
 
 	if (s3wake && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) {
 		printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n");
 		stage_cache_load_stage(STAGE_REFCODE, &fsps);
 		if (fsp_validate_component(hdr, prog_rdev(&fsps)) != CB_SUCCESS)
 			die("On resume fsps header is invalid\n");
-		do_silicon_init(hdr);
+		load_done = 1;
 		return;
 	}
 
-
 	if (cbfs_boot_locate(&file_desc, name, NULL)) {
 		printk(BIOS_ERR, "Could not locate %s in CBFS\n", name);
 		die("FSPS not available!\n");
@@ -116,6 +119,11 @@
 
 	/* Signal that FSP component has been loaded. */
 	prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL);
+	load_done = 1;
+}
 
-	do_silicon_init(hdr);
+void fsp_silicon_init(bool s3wake)
+{
+	fsps_load(s3wake);
+	do_silicon_init(&fsps_hdr);
 }