diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 30c2675..66d5cb1 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -65,7 +65,7 @@
 
 	int docking_supported;
 
-	uint8_t pcie_hotplug_map[8];
+	bool pcie_hotplug_map[8];
 
 	/* Ports which can be routed to either EHCI or xHCI.  */
 	uint32_t xhci_switchable_ports;
diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c
index b549619..d5766d8 100644
--- a/src/southbridge/intel/common/pciehp.c
+++ b/src/southbridge/intel/common/pciehp.c
@@ -4,10 +4,11 @@
 #include <acpi/acpigen.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <stdbool.h>
 
 #include "pciehp.h"
 
-void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number)
+void intel_acpi_pcie_hotplug_generator(bool *hotplug_map, int port_number)
 {
 	int port;
 	int have_hotplug = 0;
diff --git a/src/southbridge/intel/common/pciehp.h b/src/southbridge/intel/common/pciehp.h
index b4e65c4..beb210c 100644
--- a/src/southbridge/intel/common/pciehp.h
+++ b/src/southbridge/intel/common/pciehp.h
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <stdbool.h>
+
 #ifndef SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H
 #define SOUTHBRIDGE_INTEL_COMMON_PCIEHP_H
 
-void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number);
+void intel_acpi_pcie_hotplug_generator(bool *hotplug_map, int port_number);
 void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus);
 
 #endif
diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h
index ec7b977..d52a0c2 100644
--- a/src/southbridge/intel/i82801ix/chip.h
+++ b/src/southbridge/intel/i82801ix/chip.h
@@ -3,6 +3,7 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
 
+#include <stdbool.h>
 #include <stdint.h>
 
 enum {
@@ -73,7 +74,7 @@
 		uint8_t scale : 2;
 	} pcie_power_limits[6];
 
-	uint8_t pcie_hotplug_map[8];
+	bool pcie_hotplug_map[8];
 
 	/* Additional LPC IO decode ranges */
 	uint32_t gen1_dec;
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h
index ae31d4f..f12a67e 100644
--- a/src/southbridge/intel/i82801jx/chip.h
+++ b/src/southbridge/intel/i82801jx/chip.h
@@ -3,6 +3,7 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
 
+#include <stdbool.h>
 #include <stdint.h>
 
 enum {
@@ -59,7 +60,7 @@
 		uint8_t scale : 2;
 	} pcie_power_limits[6];
 
-	uint8_t pcie_hotplug_map[8];
+	bool pcie_hotplug_map[8];
 
 	/* Additional LPC IO decode ranges */
 	uint32_t gen1_dec;