commit f462b3d379198c968467053f570d6a40c9c8a715
author Angel Pons <th3fanbus@gmail.com> Wed Jan 20 00:36:31 2021 +0100
committer Angel Pons <th3fanbus@gmail.com> Sun Feb 07 20:20:00 2021 +0000
tree 06da018e6740df91f9d7fcbd9d18fa600efcc2dd
parent dd1fb4e38c209f4713d80ae192bd8f4cb4ed0e32

nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors

These accessors can be reused for several other northbridges.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/gm45/acpi/gm45.asl

diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
index fc73f24..43d73e9 100644
--- a/src/northbridge/intel/gm45/acpi/gm45.asl
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include "hostbridge.asl"
-#include "../memmap.h"
 #include <southbridge/intel/i82801ix/i82801ix.h>
 
 /* PCI Device Resource Consumption */
@@ -14,9 +13,9 @@
 	// now.
 	Name (PDRS, ResourceTemplate() {
 		Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
-		Memory32Fixed(ReadWrite, DEFAULT_MCHBAR,   0x00004000)
-		Memory32Fixed(ReadWrite, DEFAULT_DMIBAR,   0x00001000)
-		Memory32Fixed(ReadWrite, DEFAULT_EPBAR,    0x00001000)
+		Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
+		Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
+		Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE,  0x00001000)
 		Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
 		Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
 		Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH