diff --git a/src/northbridge/intel/common/Kconfig.common b/src/northbridge/intel/common/Kconfig.common
new file mode 100644
index 0000000..4f231be
--- /dev/null
+++ b/src/northbridge/intel/common/Kconfig.common
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config NORTHBRIDGE_INTEL_COMMON
+	bool
+
+if NORTHBRIDGE_INTEL_COMMON
+
+config FIXED_DMIBAR_MMIO_BASE
+	hex
+
+config FIXED_EPBAR_MMIO_BASE
+	hex
+
+config FIXED_MCHBAR_MMIO_BASE
+	hex
+
+endif # NORTHBRIDGE_INTEL_COMMON
diff --git a/src/northbridge/intel/common/fixed_bars.h b/src/northbridge/intel/common/fixed_bars.h
new file mode 100644
index 0000000..d1b005b
--- /dev/null
+++ b/src/northbridge/intel/common/fixed_bars.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H
+#define NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H
+
+_Static_assert(CONFIG_FIXED_MCHBAR_MMIO_BASE != 0, "MCHBAR base address is zero");
+_Static_assert(CONFIG_FIXED_DMIBAR_MMIO_BASE != 0, "DMIBAR base address is zero");
+_Static_assert(CONFIG_FIXED_EPBAR_MMIO_BASE  != 0,  "EPBAR base address is zero");
+
+#include <stdint.h>
+
+#define MCHBAR8(x)	(*((volatile u8  *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x))))
+#define MCHBAR16(x)	(*((volatile u16 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x))))
+#define MCHBAR32(x)	(*((volatile u32 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x))))
+
+#define DMIBAR8(x)	(*((volatile u8  *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x))))
+#define DMIBAR16(x)	(*((volatile u16 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x))))
+#define DMIBAR32(x)	(*((volatile u32 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x))))
+
+#define EPBAR8(x)	(*((volatile u8  *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x))))
+#define EPBAR16(x)	(*((volatile u16 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x))))
+#define EPBAR32(x)	(*((volatile u32 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x))))
+
+#endif	/* ! NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H */