acpi: Rename acpi_create_dmar_drhd
For most of SoCs, DRHD is by default with the size of 4KB. However,
larger sizes are allowed as well. Rename acpi_create_dmar_drhd to
acpi_create_dmar_drhd_4k to support the default case while a later
patch will re-add acpi_create_dmar_drhd with a size parameter.
TEST=intel/archercity CRB
Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c
index 246fe9a..70f0736 100644
--- a/src/northbridge/intel/gm45/acpi.c
+++ b/src/northbridge/intel/gm45/acpi.c
@@ -25,13 +25,13 @@
PCI_CLASS_REVISION);
unsigned long tmp = current;
- current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1);
+ current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE1);
current += acpi_create_dmar_ds_pci(current, 0, 0x1b, 0);
acpi_dmar_drhd_fixup(tmp, current);
if (stepping != STEPPING_B2 && igd_active) {
tmp = current;
- current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE2);
+ current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE2);
current += acpi_create_dmar_ds_pci(current, 0, 0x2, 0);
current += acpi_create_dmar_ds_pci(current, 0, 0x2, 1);
acpi_dmar_drhd_fixup(tmp, current);
@@ -39,7 +39,7 @@
if (me_active) {
tmp = current;
- current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE3);
+ current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE3);
current += acpi_create_dmar_ds_pci(current, 0, 0x3, 0);
current += acpi_create_dmar_ds_pci(current, 0, 0x3, 1);
current += acpi_create_dmar_ds_pci(current, 0, 0x3, 2);
@@ -47,7 +47,7 @@
acpi_dmar_drhd_fixup(tmp, current);
}
- current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4);
+ current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4);
/* TODO: reserve GTT for 0.2.0 and 0.2.1? */
return current;
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index f3c107b..bd2f719 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -28,7 +28,7 @@
if (emit_igd) {
const unsigned long tmp = current;
- current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
+ current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current);
@@ -37,7 +37,7 @@
/* VTVC0BAR has to be set, enabled, and in 32-bit space */
if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) {
const unsigned long tmp = current;
- current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
+ current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
PCH_IOAPIC_PCI_BUS,
PCH_IOAPIC_PCI_SLOT, 0);
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index 8be161e..3ffab4d 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -34,14 +34,14 @@
if (igfx && igfx->enabled) {
const unsigned long tmp = current;
- current += acpi_create_dmar_drhd(current, 0, 0, GFXVT_BASE);
+ current += acpi_create_dmar_drhd_4k(current, 0, 0, GFXVT_BASE);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current);
}
{
const unsigned long tmp = current;
- current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE);
+ current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE);
current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
PCH_IOAPIC_PCI_BUS,