commit f38f30a3de453c877eb593280419da612b220d17
author Kyösti Mälkki <kyosti.malkki@gmail.com> Fri Nov 25 06:22:10 2022 +0200
committer Kyösti Mälkki <kyosti.malkki@gmail.com> Sun Nov 27 20:42:30 2022 +0000
tree 71a630e0833bab5f7a3fe4930710677f27eeab7d
parent 5b92aa9c64c74194d1e405e0c8ec9f827f7c4fc6

Revert "sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros"

This reverts commit 9f0e21a4dae864809e9651403ab5bad48e784bee.

It should be allowed for i82801gx/early_init.c to have
   #include <southbridge/intel/common/pmutil.h>

But there is a conflict:

src/southbridge/intel/common/pmutil.h:
   #define TCO1_CNT  0x68
src/southbridge/intel/common/tco.h:
   #define TCO1_CNT  0x08

Followup works resolve the difficulties around the offset
0x60 used for TCO register bank, tree-wide.

Change-Id: I827558a0e0ef1c4d1f866756df51cd1b2abfc7a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/southbridge/intel/i82801gx/lpc.c

diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index f8a2dac8..fd0a203 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -20,7 +20,6 @@
 #include <southbridge/intel/common/hpet.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/common/spi.h>
-#include <southbridge/intel/common/tco.h>
 
 #include "chip.h"
 #include "i82801gx.h"
@@ -428,9 +427,9 @@
 	pci_or_config16(dev, GEN_PMCON_1, 1 << 4);
 
 	/* TCO_Lock */
-	tco1_cnt = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT);
+	tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT);
 	tco1_cnt |= (1 << 12); /* TCO lock */
-	write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, tco1_cnt);
+	outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT);
 
 	/* Indicate finalize step with post code */
 	post_code(POST_OS_BOOT);