diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 3b07a15..1e58dfd 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -158,7 +158,7 @@
 	u32 codec_mask;
 	u32 reg32;
 
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res)
 		return;
 
diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c
index 177d581..cf322eb 100644
--- a/src/southbridge/intel/bd82x6x/me_common.c
+++ b/src/southbridge/intel/bd82x6x/me_common.c
@@ -336,7 +336,7 @@
 	struct mei_csr host;
 
 	/* Find the MMIO base for the ME interface */
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res || res->base == 0 || res->size == 0) {
 		printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
 		return -1;
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
index 839b0c3..0ae1f4a 100644
--- a/src/southbridge/intel/bd82x6x/smbus.c
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -19,7 +19,7 @@
 	pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
 
 	/* Set Receive Slave Address */
-	res = find_resource(dev, PCI_BASE_ADDRESS_4);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_4);
 	if (res)
 		smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
 }
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 8bc45f6..2764861 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -43,7 +43,7 @@
 	/* Enable writes to protected registers. */
 	pci_write_config8(dev, 0x80, access_cntl | 1);
 
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (res) {
 		/* Number of ports and companion controllers.  */
 		reg32 = read32((void *)(uintptr_t)(res->base + 4));
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index 0473de6..cc5d345 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -186,7 +186,7 @@
 	// Docking not supported
 	pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
 
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res)
 		return;
 
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index abb0e2e..d0d8b3b 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -130,7 +130,7 @@
 		/* Interrupt Pin is set by D31IP.PIP */
 		pci_write_config8(dev, INTR_LN, 0x0a);
 
-		struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5);
+		struct resource *ahci_res = probe_resource(dev, PCI_BASE_ADDRESS_5);
 		if (ahci_res != NULL)
 			/* write AHCI GHC_PI register */
 			write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented);
diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c
index 90d784c..2646cbc 100644
--- a/src/southbridge/intel/i82801ix/azalia.c
+++ b/src/southbridge/intel/i82801ix/azalia.c
@@ -179,7 +179,7 @@
 	/* Lock some R/WO bits by writing their current value. */
 	pci_update_config32(dev, 0x74, ~0, 0);
 
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res)
 		return;
 
diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c
index 885c332..500c004 100644
--- a/src/southbridge/intel/i82801jx/azalia.c
+++ b/src/southbridge/intel/i82801jx/azalia.c
@@ -179,7 +179,7 @@
 	/* Lock some R/WO bits by writing their current value. */
 	pci_update_config32(dev, 0x74, ~0, 0);
 
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res)
 		return;
 
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 683715f..5eb1ac3 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -158,7 +158,7 @@
 	u32 reg32;
 
 	/* Find base address */
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res)
 		return;
 
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 20b8aac..74b3861 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -395,7 +395,7 @@
 	u16 reg16;
 
 	/* Find the MMIO base for the ME interface */
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res || res->base == 0 || res->size == 0) {
 		printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
 		return -1;
diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c
index 12734a0..6652325 100644
--- a/src/southbridge/intel/ibexpeak/smbus.c
+++ b/src/southbridge/intel/ibexpeak/smbus.c
@@ -19,7 +19,7 @@
 	pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
 
 	/* Set Receive Slave Address */
-	res = find_resource(dev, PCI_BASE_ADDRESS_4);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_4);
 	if (res)
 		smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
 }
diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c
index 142d3c7..b96833c 100644
--- a/src/southbridge/intel/ibexpeak/thermal.c
+++ b/src/southbridge/intel/ibexpeak/thermal.c
@@ -14,7 +14,7 @@
 	u8 *base;
 	printk(BIOS_DEBUG, "Thermal init start.\n");
 
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res)
 		return;
 
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index a2adc5a..3de8c33 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -36,7 +36,7 @@
 	/* Enable writes to protected registers. */
 	pci_write_config8(dev, 0x80, access_cntl | 1);
 
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (res) {
 		/* Number of ports and companion controllers.  */
 		reg32 = read32((u32 *)(uintptr_t)(res->base + 4));
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index 27ee924..fe5c4c9 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -101,7 +101,7 @@
 	u32 codec_mask;
 
 	/* Find base address */
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res)
 		return;
 
diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c
index 886fd90..c2f1db2 100644
--- a/src/southbridge/intel/lynxpoint/me.c
+++ b/src/southbridge/intel/lynxpoint/me.c
@@ -670,7 +670,7 @@
 	struct mei_csr host;
 
 	/* Find the MMIO base for the ME interface */
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res || res->base == 0 || res->size == 0) {
 		printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
 		return -1;
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 34f8c78..0aa683d 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -166,10 +166,10 @@
 	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 
 	/* Find BAR0 and BAR1 */
-	bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
+	bar0 = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!bar0)
 		return;
-	bar1 = find_resource(dev, PCI_BASE_ADDRESS_1);
+	bar1 = probe_resource(dev, PCI_BASE_ADDRESS_1);
 	if (!bar1)
 		return;
 
diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c
index d55aa6e..f41e322 100644
--- a/src/southbridge/intel/lynxpoint/smbus.c
+++ b/src/southbridge/intel/lynxpoint/smbus.c
@@ -18,7 +18,7 @@
 	pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
 
 	/* Set Receive Slave Address */
-	res = find_resource(dev, PCI_BASE_ADDRESS_4);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_4);
 	if (res)
 		smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
 }