commit f2dfef01e1fdf9d8218f0bc6ecfc3f943dc4d2a1
author WANG Siyuan <wangsiyuanbuaa@gmail.com> Wed May 20 14:41:01 2015 +0800
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Sat Jun 13 02:22:49 2015 +0200
tree 3c0b66ab3395249ddfa4524ebc80bdf3007acc89
parent 597ee56261c75c4e621a83e5999bc84e772ed53f

southbridge/amd/pi: Add support for new AMD southbridge Kern

Kern is the southbridge of AMD Merlin Falcon(Carrizo).
This add support of HD audio, lpc, sata and usb for Kern.

Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10418
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/include/device/pci_ids.h

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index a02a27c..13e66db 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -427,6 +427,13 @@
 #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV13    0x5A1E
 #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8     0x5A21
 
+#define PCI_DEVICE_ID_AMD_CZ_HDA        0x157A
+#define PCI_DEVICE_ID_AMD_CZ_LPC        0x790E
+#define PCI_DEVICE_ID_AMD_CZ_SATA       0x7900
+#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI  0x7901
+#define PCI_DEVICE_ID_AMD_CZ_USB_0      0x7907
+#define PCI_DEVICE_ID_AMD_CZ_USB_1      0x7908
+
 #define PCI_VENDOR_ID_VLSI		0x1004
 #define PCI_DEVICE_ID_VLSI_82C592	0x0005
 #define PCI_DEVICE_ID_VLSI_82C593	0x0006