blob: 2e3fa7ac449bd6c4b229c4019d505c2ac0f0d35d [file] [log] [blame]
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corp.
* (Written by Lijian Zhao <lijian.zhao@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, /* DSDT revision: ACPI v2.0 and up */
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 /* OEM revision */
)
{
Scope (\_SB) {
Device (PCI0)
{
Name (_HID, EISAID ("PNP0A08")) /* PCIe */
}
}
/* Chipset specific sleep states */
#include <soc/intel/apollolake/acpi/sleepstates.asl>
}