mb/intel/archercity_crb: Fix build for specific configurations
Guard OCP functions calls to allow builds without OCP drivers.
Change-Id: Ie9a82387366a8bb3387bcba3ec7a4c7f0100f78c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/mainboard/intel/archercity_crb/romstage.c b/src/mainboard/intel/archercity_crb/romstage.c
index ff56f59..9189099 100644
--- a/src/mainboard/intel/archercity_crb/romstage.c
+++ b/src/mainboard/intel/archercity_crb/romstage.c
@@ -11,7 +11,8 @@
void mainboard_ewl_check(void)
{
- get_ewl();
+ if (CONFIG(OCP_EWL))
+ get_ewl();
}
static void mainboard_config_iio(FSPM_UPD *mupd)
@@ -36,21 +37,23 @@
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
/* Setup FSP log */
- mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG,
- FSP_LOG_DEFAULT);
- if (mupd->FspmConfig.SerialIoUartDebugEnable) {
- mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range(
- FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4);
- /* If serialDebugMsgLvl less than 1, disable FSP memory train results */
- if (mupd->FspmConfig.serialDebugMsgLvl <= 1) {
- printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n");
- mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0;
+ if (CONFIG(OCP_VPD)) {
+ mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG,
+ FSP_LOG_DEFAULT);
+ if (mupd->FspmConfig.SerialIoUartDebugEnable) {
+ mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range(
+ FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4);
+ /* If serialDebugMsgLvl less than 1, disable FSP memory train results */
+ if (mupd->FspmConfig.serialDebugMsgLvl <= 1) {
+ printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n");
+ mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0;
+ }
}
- }
- /* FSP Dfx PMIC Secure mode */
- mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range(
- FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2);
+ /* FSP Dfx PMIC Secure mode */
+ mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range(
+ FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2);
+ }
/* Set Rank Margin Tool to disable. */
mupd->FspmConfig.EnableRMT = 0x0;
diff --git a/src/mainboard/intel/archercity_crb/util.c b/src/mainboard/intel/archercity_crb/util.c
index 5197b23..0dac1e1 100644
--- a/src/mainboard/intel/archercity_crb/util.c
+++ b/src/mainboard/intel/archercity_crb/util.c
@@ -4,7 +4,7 @@
#include <soc/chip_common.h>
#include <soc/util.h>
-#if CONFIG(SOC_INTEL_HAS_CXL)
+#if CONFIG(SOC_INTEL_HAS_CXL) && CONFIG(OCP_VPD)
enum xeonsp_cxl_mode get_cxl_mode(void)
{
int ocp_cxl_mode = get_cxl_mode_from_vpd();