diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index c21e321..357a963 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -15,6 +15,7 @@
 #include <console/console.h>
 #include <stdlib.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <spd.h>
 
 #include "raminit.h"
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index 1b86012..afe11bb 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -15,6 +15,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cbmem.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 317f087..0032356 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -13,6 +13,7 @@
 
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 70a0d66..276307d 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -27,6 +27,7 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <lib.h>
 #include <stdlib.h>
 #include <commonlib/helpers.h>
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c
index 25560dd..ca439a0 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.c
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c
@@ -18,6 +18,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <stdint.h>
 #include <delay.h>
 #include <cpu/intel/fsp_model_406dx/model_406dx.h>
diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c
index 91e0179..c93d3bd 100644
--- a/src/northbridge/intel/fsp_rangeley/port_access.c
+++ b/src/northbridge/intel/fsp_rangeley/port_access.c
@@ -18,6 +18,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge.h"
diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c
index dc59372..301743ce 100644
--- a/src/northbridge/intel/gm45/acpi.c
+++ b/src/northbridge/intel/gm45/acpi.c
@@ -21,6 +21,7 @@
 #include <arch/acpigen.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include "gm45.h"
 
 unsigned long acpi_fill_mcfg(unsigned long current)
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index 8a61e1c..5b1c301 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -12,6 +12,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 /* Just re-define these instead of including gm45.h. It blows up romcc. */
 #define D0F0_PCIEXBAR_LO 0x60
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index c2e4aea..723a43f 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -15,6 +15,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include "gm45.h"
 
 void gm45_early_init(void)
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index c987cb3..9f919cf 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -16,6 +16,7 @@
 
 #include <types.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <halt.h>
 #include "gm45.h"
 
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index 45144aa..b0e2ba9 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include <pc80/mc146818rtc.h>
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index f424564..642c877 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -18,6 +18,7 @@
 #include <string.h>
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <arch/acpi.h>
 
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 791559b..fddb1fe 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -16,6 +16,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 5d6c182..1a6e3de 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -18,6 +18,7 @@
 #include <stddef.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index af1a46d..c1ef30e 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 176c16a..d4209dc 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -18,6 +18,7 @@
 #include <stdlib.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <device/device.h>
 #include <spd.h>
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index 6d652bb..7335ac9 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -19,6 +19,7 @@
 #include <romstage_handoff.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/bist.h>
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index f655c3b..d92e858 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -20,6 +20,7 @@
 #include <arch/acpi.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include "haswell.h"
 #include <southbridge/intel/lynxpoint/pch.h>
 
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index a25f363..d7f4e6e 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -12,6 +12,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 /* Just re-define this instead of including haswell.h. It blows up romcc. */
 #define PCIEXBAR	0x60
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index be83894..a04b3f4 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <bootmode.h>
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c
index d3e88f2..24fbb64b 100644
--- a/src/northbridge/intel/haswell/ram_calc.c
+++ b/src/northbridge/intel/haswell/ram_calc.c
@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cbmem.h>
 #include "haswell.h"
 
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 1bc3110..376e63f 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -18,6 +18,7 @@
 #include <string.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
 #include "haswell.h"
 
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index cff3ade..b4d92b0 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -13,6 +13,7 @@
 
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <spd.h>
 #include "raminit.h"
 
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 4b1141c..ae89766 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -13,6 +13,7 @@
 
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c
index 962f3ba..3207688 100644
--- a/src/northbridge/intel/i440bx/ram_calc.c
+++ b/src/northbridge/intel/i440bx/ram_calc.c
@@ -16,6 +16,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <commonlib/helpers.h>
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 49994ed..0c9496b 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include "i440bx.h"
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index 053815b..f817cdf 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -20,6 +20,7 @@
 #include <arch/acpigen.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include "i945.h"
 
 unsigned long acpi_fill_mcfg(unsigned long current)
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 5296d52..1c00e8b 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -12,6 +12,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 /* Just re-define this instead of including i945.h. It blows up romcc. */
 #define PCIEXBAR	0x48
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index c52f2a6..370131f 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -16,6 +16,7 @@
 
 #include <spd.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include "i945.h"
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index b82812e..d9d88bb 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -18,6 +18,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <cbmem.h>
 #include <halt.h>
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 7a2a489..3a01940 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -18,6 +18,7 @@
 #include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <pc80/mc146818rtc.h>
 #include <edid.h>
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 7c209dc..1dff3d1 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -16,6 +16,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index fd37aea..c797d42 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cbmem.h>
 #include "i945.h"
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index dece9bf..c6a2e05 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -17,6 +17,7 @@
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <device/pci_def.h>
+#include <device/pci_ops.h>
 #include <device/device.h>
 #include <lib.h>
 #include <pc80/mc146818rtc.h>
diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
index 08fc09c..462cdc0 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -21,6 +21,7 @@
 #include <types.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include "nehalem.h"
 
 unsigned long acpi_fill_mcfg(unsigned long current)
diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c
index 807e919..c37aa3a 100644
--- a/src/northbridge/intel/nehalem/bootblock.c
+++ b/src/northbridge/intel/nehalem/bootblock.c
@@ -12,6 +12,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 static void bootblock_northbridge_init(void)
 {
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index ac0ed45..2c958a4 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -19,6 +19,7 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include <cpu/x86/msr.h>
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index fbe6c11..43ec6ed 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -18,6 +18,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <stdint.h>
 #include <delay.h>
 #include <cpu/intel/model_2065x/model_2065x.h>
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index baf087e..3df6f81 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -18,6 +18,7 @@
 
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index c730b5e..9812e53 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -18,6 +18,7 @@
 #include <console/console.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c
index a08ac1b..6aefc9b 100644
--- a/src/northbridge/intel/nehalem/smi.c
+++ b/src/northbridge/intel/nehalem/smi.c
@@ -17,6 +17,7 @@
 #include <string.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include "nehalem.h"
 
 #include <cpu/intel/smm/gen1/smi.h>
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
index 1fab845..f3eab49 100644
--- a/src/northbridge/intel/pineview/bootblock.c
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -12,6 +12,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #define PCIEXBAR 0x60
 #define MMCONF_256_BUSSES 16
 #define ENABLE 1
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index 8974428..11dc203 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -18,6 +18,7 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <device/pci.h>
 #include <halt.h>
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index ec2c902..94aed89 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -17,6 +17,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index 21b926b..cf9db98 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index ed633fd..1b2ad8d 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <delay.h>
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index 10ac0f5..0d2cc36 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -20,6 +20,7 @@
 #include <lib.h>
 #include <timestamp.h>
 #include <console/console.h>
+#include <device/pci_ops.h>
 #include <cbmem.h>
 #include <romstage_handoff.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index c274318..4afb546 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -21,6 +21,7 @@
 #include <arch/acpi.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include "sandybridge.h"
 #include <southbridge/intel/bd82x6x/pch.h>
 
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index 05b0c75..c35a49a 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -12,6 +12,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 /* Just re-define this instead of including sandybridge.h. It blows up romcc. */
 #define PCIEXBAR	0x60
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index f8ecc1a..01787f1 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -18,6 +18,7 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <device/pci_def.h>
 #include <elog.h>
diff --git a/src/northbridge/intel/sandybridge/iommu.c b/src/northbridge/intel/sandybridge/iommu.c
index 017c732..26bbdf9 100644
--- a/src/northbridge/intel/sandybridge/iommu.c
+++ b/src/northbridge/intel/sandybridge/iommu.c
@@ -17,6 +17,7 @@
 #include <stdint.h>
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci_def.h>
 
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 0d644ca..4d00d73 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -17,6 +17,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <stdint.h>
 #include <delay.h>
 #include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c
index bb88c7a..53fb4d3 100644
--- a/src/northbridge/intel/sandybridge/pcie.c
+++ b/src/northbridge/intel/sandybridge/pcie.c
@@ -17,6 +17,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pciexp.h>
 #include <device/pci_ids.h>
 #include <assert.h>
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
index 00e3e78..0e5127d 100644
--- a/src/northbridge/intel/sandybridge/ram_calc.c
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -17,6 +17,7 @@
 
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 5f7fd0a..115d515 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -21,6 +21,7 @@
 #include <string.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cbmem.h>
 #include <halt.h>
 #include <timestamp.h>
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 4897581..afdd908 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -19,6 +19,7 @@
 #include <string.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <northbridge/intel/sandybridge/chip.h>
 #include <device/pci_def.h>
 #include <delay.h>
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index af9b490..6142388 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -18,6 +18,7 @@
 #include <bootmode.h>
 #include <string.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
 #include <cbfs.h>
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 26f4977..c979897 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -19,6 +19,7 @@
 #include <string.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cpu/x86/lapic.h>
 #include <timestamp.h>
 #include "sandybridge.h"
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index 9629d88..b470e95 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include "iomap.h"
 #include "x4x.h"
 
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index c6eb383..9cb3df3 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -16,6 +16,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include "iomap.h"
 #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
 #include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 4b5a754..c168e38 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -17,6 +17,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 6484326..ff3c31b 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -22,6 +22,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 1fd6004..ea00f29 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 5c5dafa..ffa861e 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -17,6 +17,7 @@
 #include <assert.h>
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <commonlib/helpers.h>
 #include <delay.h>