commit f1b58b78351d7ed220673e688a2f7bc9e96da4e2
author Kyösti Mälkki <kyosti.malkki@gmail.com> Fri Mar 01 13:43:02 2019 +0200
committer Patrick Georgi <pgeorgi@google.com> Fri Mar 01 20:32:15 2019 +0000
tree d8aae223f0e426f189cb4750b972a31e09d46b88
parent 44e89af6e609874f2f18d30f1e66dce8b5a98eff

device/pci: Fix PCI accessor headers

PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.

Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/northbridge/intel/haswell/acpi.c

diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index f655c3b..d92e858 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -20,6 +20,7 @@
 #include <arch/acpi.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include "haswell.h"
 #include <southbridge/intel/lynxpoint/pch.h>
 

src/northbridge/intel/haswell/bootblock.c

diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index a25f363..d7f4e6e 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -12,6 +12,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 /* Just re-define this instead of including haswell.h. It blows up romcc. */
 #define PCIEXBAR	0x60

src/northbridge/intel/haswell/gma.c

diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index be83894..a04b3f4 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <bootmode.h>

src/northbridge/intel/haswell/ram_calc.c

diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c
index d3e88f2..24fbb64b 100644
--- a/src/northbridge/intel/haswell/ram_calc.c
+++ b/src/northbridge/intel/haswell/ram_calc.c
@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cbmem.h>
 #include "haswell.h"
 

src/northbridge/intel/haswell/report_platform.c

diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 1bc3110..376e63f 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -18,6 +18,7 @@
 #include <string.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
 #include "haswell.h"