riscv: enable counters via m[us]counteren
The user and supervisor counters could not be safely enabled
before as the register numbers were not finalized. Now that
everyone agrees, we can enable them. Until we are sure the
toolchains are caught up, we use the hardcode name with
the register names in comments. As soon as toolchains
settle down we'll do one more pass and convert to
the symbolic names.
Tested on lowrisc bitstream and SPIKE simulator.
Signed-off-by: Ronald G. Minnich <firstname.lastname@example.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Alex Bradbury <email@example.com>
Reviewed-by: Jonathan Neuschäfer <firstname.lastname@example.org>
Reviewed-by: Andrew Waterman <email@example.com>
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index aceb72e..2c440d2 100644
@@ -310,14 +310,12 @@
- /* Enable all user/supervisor-mode counters */
- /* We'll turn these on once lowrisc gets their bitstream up to
- * 1.9. Right now there's no agreement on the values for these
- * architectural registers.
- // write_csr(mscounteren, 0b111);
- // write_csr(mucounteren, 0b111);
- // for SPIKE:
- // write_csr(/*mscounteren*/0x321, 0b111);
+ // Enable all user/supervisor-mode counters using
+ // v1.9.1 register addresses.
+ // They moved from the earlier spec.
+ // Until we trust our toolchain use the hardcoded constants.
+ // These were in flux and people who get the older toolchain
+ // will have difficult-to-debug failures.
+ write_csr(/*mucounteren*/0x320, 7);
+ write_csr(/*mscounteren*/0x321, 7);