tree f99bbe11deb064a409ae7e74398a3248827c1be6
parent 385f4bb965cd0f67958d77389d5185a38cb3c9d8
author Mario Scheithauer <mario.scheithauer@siemens.com> 1684759467 +0200
committer Felix Held <felix-coreboot@felixheld.de> 1685634082 +0000

soc/intel/apollolake: Make SATA speed limit configurable

In cases where there are limitations on the mainboard it can be
necessary to limit the used SATA speed even though both, the SATA
controller and disk drive support a higher speed rate. The FSP parameter
'SpeedLimit' allows to set the speed limit.

It should be noted that Gen 3 equals the default value '0'. This means
that inside FSP the same code is executed.

This patch provides a chip config so that this FSP parameter can be
set as needed in the devicetree on mainboard level.

Change-Id: I9c3eda0649546e3a40eb24a015b7c6efd8f90e0f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75364
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>