AMD boards: Fix includes for microcode updates
No ROMCC involved, no need to include .c files in romstage.c.
Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4501
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 2487b2f..5168662 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -70,11 +70,7 @@
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
-#include "cpu/amd/microcode/microcode.c"
-
-#if CONFIG_UPDATE_CPU_MICROCODE
-#include "cpu/amd/model_10xxx/update_microcode.c"
-#endif
+#include "cpu/amd/microcode.h"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@@ -127,9 +123,8 @@
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
-#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
-#endif
+
post_code(0x33);
cpuSetAMDMSR();