soc/amd/common/block/cpu/mca/mcax: add comment about McaXEnable bit
TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN
APU that the McaXEnable bit is set in the CONFIG registers of all used
MCAX banks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/amd/common/block/cpu/mca/mcax.c b/src/soc/amd/common/block/cpu/mca/mcax.c
index a4b5c59..46c72f0 100644
--- a/src/soc/amd/common/block/cpu/mca/mcax.c
+++ b/src/soc/amd/common/block/cpu/mca/mcax.c
@@ -7,6 +7,9 @@
#include <types.h>
#include "mca_common_defs.h"
+/* The McaXEnable bit in the config registers of the available MCAX banks is already set by the
+ FSP, so no need to set it here again. */
+
bool mca_skip_check(void)
{
/* On Zen-based CPUs/APUs the MCA(X) status register have a defined state even in the