google/oak: Initialize i2c bus timing register for TPM and external buck
BRANCH=none
BUG=none
TEST=build pass and boot to oak kernel
Change-Id: Id2c3bbb70a1de54a56ee04ecda76178b1bdf1a4d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9
Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9
Original-Signed-off-by: jun.gao <jun.gao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319031
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index efb489f..49cf5dd 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -18,6 +18,7 @@
#include <bootblock_common.h>
#include <delay.h>
#include <soc/gpio.h>
+#include <soc/i2c.h>
#include <soc/mt6391.h>
#include <soc/pericfg.h>
#include <soc/pinmux.h>
@@ -78,6 +79,9 @@
/* set nor related GPIO */
nor_set_gpio_pinmux();
+ /* Init i2c bus 2 Timing register for TPM */
+ mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
+
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
setup_chromeos_gpios();