tree d8241d6f3843f4f693a4d19170efa7c1d79418c7
parent 8127dc41d1fde1118cdbe3bf6b592312b5b85c02
author Marc Jones <marc.jones@amd.com> 1208906873 +0000
committer Marc Jones <marc.jones@amd.com> 1208906873 +0000

Find matching settings for each CPUs FID, VID, and P-state registers and initialize them. 

Supports single and split plane systems. Set P0 on all cores for best performance.
All APs will be in hlt(C1).

The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1