commit efbfdd2d60043b75d87f4149f28eceafa19643d8
author Subrata Banik <subrata.banik@intel.com> Mon Feb 26 14:49:00 2018 +0530
committer Martin Roth <martinroth@google.com> Fri Mar 09 21:40:32 2018 +0000
tree dff39e2cfd8e905f343d1d1f4e64e16c2526aac7
parent d83faceefa77e9a769a7e6de4ad5313d5afc422a

soc/intel/skylake: Move PCR DMI programming into bootblock

As per PCH BWG 2.5.16, set up LPC IO Enables PCR[DMI] + 2774h bit
[15:0] to the same value program in LPC PCI offset 82h. Also this
cycle decoding is only allowed to set when SRLOCK is not set.

Hence move the required programming from lpc.c to pch.c.

Also only enable COM port ranges if CONFIG_DRIVERS_UART_8250IO
Kconfig is selected.

Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/skylake/bootblock/pch.c

diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 34cfaa3..521a1b7 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -36,6 +36,8 @@
 #include <soc/pmc.h>
 #include <soc/smbus.h>
 
+#define PCR_DMI_DMICTL		0x2234
+#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
 #define PCR_DMI_ACPIBA		0x27B4
 #define PCR_DMI_ACPIBDID	0x27B8
 #define PCR_DMI_PMBASEA		0x27AC
@@ -158,14 +160,39 @@
 	outw(tcocnt, tcobase + TCO1_CNT);
 }
 
+static int pch_check_decode_enable(void)
+{
+	uint32_t dmi_control;
+
+	/*
+	 * This cycle decoding is only allowed to set when
+	 * DMICTL.SRLOCK is 0.
+	 */
+	dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
+	if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
+		return -1;
+	return 0;
+}
+
 void pch_early_iorange_init(void)
 {
+	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+			LPC_IOE_EC_62_66;
+
 	/* IO Decode Range */
-	lpc_io_setup_comm_a_b();
+	if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))
+		lpc_io_setup_comm_a_b();
 
 	/* IO Decode Enable */
-	lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
-		LPC_IOE_EC_62_66);
+	if (pch_check_decode_enable() == 0) {
+		io_enables = lpc_enable_fixed_io_ranges(io_enables);
+		/*
+		 * As per PCH BWG 2.5.16.
+		 * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
+		 * value program in LPC PCI offset 82h.
+		 */
+		pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+	}
 
 	/* Program generic IO Decode Range */
 	pch_enable_lpc();

src/soc/intel/skylake/lpc.c

diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index d0678c9..3d1dd7b 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -82,17 +82,11 @@
 
 void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
 {
-	uint16_t lpc_en;
-
 	/* Mirror these same settings in DMI PCR */
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-
-	/* LPC IO Decode Enable */
-	lpc_en = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);
-	pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en);
 }
 
 static const struct reg_script pch_misc_init_script[] = {