tree a22c88456df0343f37e7dbaf35627857ae6d9fb8
parent 34684caad56a489b26c0cf7f5f7f98cff7dc72c5
author Arthur Heymans <arthur@aheymans.xyz> 1706896193 +0100
committer Martin L Roth <gaumless@gmail.com> 1711639354 +0000

cpu/x86: Link page tables in stage if possible

When switching back and forth between 32 to 64 bit mode, for example to
call a 32-bits FSP or to call the payload, new page tables in the
respective stage will be linked.

The advantages of this approach are:
- No need to determine a good place for page tables in CBFS that does
  not overlap.
- Works with non memory mapped flash (however all coreboot targets
  currently do support this)
- If later stages can use their own page tables which fits better with
  the vboot RO/RW flow

A disadvantage is that it increases the stage size. This could be
improved upon by using 1G pages and generating the pages at runtime.

Note: qemu cannot have the page tables in the RO boot medium and needs
to relocate them at runtime. This is why keeping the existing code with
page tables in CBFS is done for now.

TEST: Booted to payload on google/vilbox and qemu/q35

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>