| commit | ee63b44c47cbb8c81ce0e173bbc12129c3edbe71 | [log] [tgz] |
|---|---|---|
| author | Reka Norman <rekanorman@google.com> | Fri Sep 16 10:39:49 2022 +1000 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Sat Sep 24 01:23:09 2022 +0000 |
| tree | e96ed996387389db2534967646a50c72b45eb95a | |
| parent | 1df1cf994aa9ebdd9d51103d2d618f6aa66df2d6 [diff] |
drivers/mrc_cache: Compare hashes instead of full data The current MRC cache update process is slow (28 ms on nissa), because cbmem is not cached in romstage. Specifically, the new MRC data returned by the FSP is stored in the FSP reserved memory in cbmem, so operations on the new data (computing the checksum, comparing to the old data) are slow. Replace the data checksum in the MRC header with a hash, and compare hashes instead of comparing the full data. This has two benefits: 1. The xxhash function is faster than computing an IP checksum (4 ms vs 14 ms on uncached data on nissa). 2. There's no need to memcmp() the full MRC data, which takes 14 ms on nissa. Before: 550:starting to load ChromeOS VPD 867,930 (4,664) 3:after RAM initialization 896,020 (28,090) 4:end of romstage 906,274 (10,254) After: 550:starting to load ChromeOS VPD 864,820 (4,649) 3:after RAM initialization 869,652 (4,831) 4:end of romstage 879,909 (10,257) BUG=b:242667207 TEST=Check that MRC caching still works as expected on nissa. Corrupt the MRC cache and check that memory is retrained. Change-Id: I1b7848d1d05e555b61e0f1cb605550dfe3449c6d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67670 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.