exynos: Set up caching in the bootblock.
This improves firmware boot time substantially. Because cbmem isn't available
yet, we need to allocate some space in sram for the ttb. Doing cache
initialization in the bootblock means we can implement this once per CPU
instead of once per mainboard.
Old-Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65938
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit c32b9b32ad933e627b9ea98434b392239b1fea73)
exynos5420: flush caches and disable MMU in resume path
This patch flushes the caches and disables the MMU before resuming.
c32b9b3 ("Set up caching in the bootblock.") had a bug where the
dcache and MMU remained enabled in the resume path. This caused
the machine to hang on resume. However, other bugs were preventing
us from testing this properly earlier on so it went unnoticed until
now.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Old-Change-Id: Ib1774f09d286a4d659da9fc2dad1d7a6fc1ebe5e
Reviewed-on: https://chromium-review.googlesource.com/67007
Reviewed-by: ron minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 4fdf9763d25f70fd1e3591f6ff9785f78dd6170d)
Squashed two related commits.
Change-Id: Ibd42b28bb06930159248130e5ceaddb3b4b6cc2a
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6511
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
diff --git a/src/arch/armv7/mmu.c b/src/arch/armv7/mmu.c
index 7d6d46a..17ad8b7 100644
--- a/src/arch/armv7/mmu.c
+++ b/src/arch/armv7/mmu.c
@@ -27,6 +27,7 @@
* SUCH DAMAGE.
*/
+#include <config.h>
#include <stdlib.h>
#include <stdint.h>
@@ -36,14 +37,12 @@
#include <arch/cache.h>
#include <arch/io.h>
-#define L1_TLB_ENTRIES 4096 /* 1 entry for each 1MB address space */
-
-static uintptr_t ttb_addr;
+static void *const ttb_buff = (void *)CONFIG_TTB_BUFFER;
void mmu_disable_range(unsigned long start_mb, unsigned long size_mb)
{
unsigned int i;
- uint32_t *ttb_entry = (uint32_t *)ttb_addr;
+ uint32_t *ttb_entry = ttb_buff;
printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n",
start_mb*MiB, start_mb*MiB + size_mb*MiB - 1);
@@ -61,7 +60,7 @@
{
unsigned int i;
uint32_t attr;
- uint32_t *ttb_entry = (uint32_t *)ttb_addr;
+ uint32_t *ttb_entry = ttb_buff;
const char *str = NULL;
/*
@@ -116,24 +115,14 @@
void mmu_init(void)
{
- unsigned int ttb_size;
- uint32_t ttbcr;
-
/*
* For coreboot's purposes, we will create a simple L1 page table
* in RAM with 1MB section translation entries over the 4GB address
* space.
* (ref: section 10.2 and example 15-4 in Cortex-A series
* programmer's guide)
- *
- * FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to
- * 512 bytes. So allocate some extra space in cbmem and fix-up the
- * pointer.
- */
- ttb_size = L1_TLB_ENTRIES * sizeof(uint32_t);
- ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size + 16*KiB);
- ttb_addr = ALIGN(ttb_addr, 16*KiB);
- printk(BIOS_DEBUG, "Translation table is @ 0x%08x\n", ttb_addr);
+ */
+ printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff);
/*
* Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0
@@ -141,16 +130,14 @@
*
* ref: Arch Ref. Manual for ARMv7-A, B3.5.4,
*/
- ttbcr = read_ttbcr();
- ttbcr &= ~(0x3);
- write_ttbcr(ttbcr);
+ write_ttbcr(read_ttbcr() & ~0x3);
/*
* Translation table base 0 address is in bits 31:14-N, where N is given
* by bits 2:0 in TTBCR (which we set to 0). All lower bits in this
* register should be zero for coreboot.
*/
- write_ttbr0(ttb_addr);
+ write_ttbr0((uintptr_t)ttb_buff);
/* disable domain-level checking of permissions */
write_dacr(~0);