nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree
Transfer all USB responsibilities to southbridge/intel/bd82x6x,
using one set of USB port configuration supplied by mainboards
in the southbridge section of their devicetree.
For MRC raminit, export southbridge_fill_pei_data() as a hook for
southbridge code to implement. With new code via this hook, bd82x6x
fills pei_data based on this one set of USB port config.
For native raminit, early_usb_init() now goes directly to the devicetree
and no longer get passed an address to it.
TEST=abuild passes for all affected boards. All USB ports still work
on asus/p8x7x-series/v/p8z77-m.
Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81881
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h
index 0309cf3..db6347c 100644
--- a/src/northbridge/intel/sandybridge/pei_data.h
+++ b/src/northbridge/intel/sandybridge/pei_data.h
@@ -116,4 +116,5 @@
int ddr_refresh_rate_config;
} __packed;
+void southbridge_fill_pei_data(struct pei_data *pei_data);
#endif
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index b9279f3..98b3028 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -252,11 +252,6 @@
}
}
-static void southbridge_fill_pei_data(struct pei_data *pei_data)
-{
- /* This will move to southbridge later. */
-}
-
static void devicetree_fill_pei_data(struct pei_data *pei_data)
{
const struct northbridge_intel_sandybridge_config *cfg = config_of_soc();
@@ -290,9 +285,6 @@
}
}
memcpy(pei_data->ts_addresses, cfg->ts_addresses, sizeof(pei_data->ts_addresses));
-
- memcpy(pei_data->usb_port_config, cfg->usb_port_config,
- sizeof(pei_data->usb_port_config));
}
static void spd_fill_pei_data(struct pei_data *pei_data)
@@ -374,7 +366,7 @@
.nmode = cfg->nmode,
.ddr_refresh_rate_config = cfg->ddr_refresh_rate_config,
.usb3.mode = cfg->usb3.mode,
- .usb3.hs_port_switch_mask = cfg->usb3.hs_port_switch_mask,
+ /* .usb3.hs_port_switch_mask = native config->xhci_switchable_ports */
.usb3.preboot_support = cfg->usb3.preboot_support,
.usb3.xhci_streams = cfg->usb3.xhci_streams,
};
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 56dc677..86569c1 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -58,7 +58,7 @@
/* When using MRC, USB is initialized by MRC */
if (CONFIG(USE_NATIVE_RAMINIT)) {
- early_usb_init(mainboard_usb_ports);
+ early_usb_init();
}
/* Perform some early chipset init needed before RAM initialization can work */