mb/intel/adlrvp: Enable HECI1 communication
The patch enables HECI1 interface to allow OS applications to communicate
with CSE.
BUG=None
TEST=Build and boot ADLRVP. Run lspci and check pcie device (00:16.0)
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I34ff842481bdfc7933a76555ff0fd70f4fbbb9a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index cade987..57d78de 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -12,6 +12,9 @@
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
+ # Enable HECI1 interface
+ register "HeciEnabled" = "1"
+
# FSP configuration
# Enable CNVi BT