commit | ed3496730322286370b956e3eeb038ee56a41c74 | [log] [tgz] |
---|---|---|
author | Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> | Tue Apr 21 19:09:43 2020 +0530 |
committer | Patrick Georgi <pgeorgi@google.com> | Mon May 18 07:15:59 2020 +0000 |
tree | 2f2d81ee096d8b6bd4edcd6c6242dce3c17ccfdd | |
parent | 2abe9cf2d7bc067d07e35f214930a2fb8047d194 [diff] |
soc/intel/jasperlake: Add function to display ME firmware status info Add function to display ME Host Firmware Status registers. Make use of print_me_fw_version() from CSE lib to print ME firmware version information. Add manufacturing mode field in HFSTS1 register for JSL in place of, spi_protection_mode in TGL. BUG=None BRANCH=None TEST=Build and boot jslrvp. In coreboot logs, ME info can be seen. ME: Version: 13.5.0.7049 ME: HFSTS1 : 0x90006255 ME: HFSTS2 : 0x82100136 ME: HFSTS3 : 0x00000020 ME: HFSTS4 : 0x00004800 ME: HFSTS5 : 0x00000000 ME: HFSTS6 : 0x00400006 ME: Manufacturing Mode : YES ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: D0i3 Support : YES ME: Low Power State Enabled : NO ME: CPU Replaced : YES ME: CPU Replacement Valid : YES ME: Current Working State : 5 ME: Current Operation State : 1 ME: Current Operation Mode : 0 ME: Error Code : 6 ME: CPU Debug Disabled : YES ME: TXT Support : NO Change-Id: Ic6b1c9410db8f06ac24fd997772b2ede04264bee Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.