soc/intel/tigerlake: Enable support for common IRQ block
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows tigerlake boards to dynamically assign PCI IRQs. This means not
relying on FSP defaults, which eliminates the problem of PCI IRQs
interfering with GPIO IRQs routed to the same IRQ, when both have
selected IO-APIC routing.
BUG=b:171580862
TEST=on delbin, grep 'IO-APIC' /proc/interrupts (compressed to fit)
0: 6 0 0 0 IO-APIC 2-edge timer
1: 0 35 0 0 IO-APIC 1-edge i8042
8: 0 0 0 0 IO-APIC 8-edge rtc0
9: 0 601 0 0 IO-APIC 9-fasteoi acpi
14: 1 0 0 0 IO-APIC 14-fasteoi INT34C5:00
20: 0 0 0 516 IO-APIC 20-fasteoi idma64.6, ttyS0
28: 0 395 0 0 IO-APIC 28-fasteoi idma64.0, i2c_design
29: 0 0 1654 0 IO-APIC 29-fasteoi idma64.1, i2c_design
30: 0 0 0 0 IO-APIC 30-fasteoi idma64.2, i2c_design
31: 0 0 0 0 IO-APIC 31-fasteoi idma64.3, i2c_design
32: 0 0 0 0 IO-APIC 32-fasteoi idma64.4, i2c_design
33: 0 0 14469 0 IO-APIC 33-fasteoi idma64.5, i2c_design
35: 0 18494 0 0 IO-APIC 35-edge cr50_spi
36: 95705 0 0 0 IO-APIC 36-fasteoi idma64.7, pxa2xx-spi
37: 0 0 1978 0 IO-APIC 37-fasteoi idma64.8, pxa2xx-spi
51: 1865 0 0 0 IO-APIC 51-fasteoi ELAN9008:00
59: 0 0 422 0 IO-APIC 59-fasteoi ELAN0000:00
116: 0 0 0 23 IO-APIC 116-fasteoi chromeos-ec
abbreviated _PRT dump:
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
If (PICM)
Package () {0x0002FFFF, 0x00, 0x00, 0x10},
Package () {0x0004FFFF, 0x00, 0x00, 0x11},
Package () {0x0005FFFF, 0x00, 0x00, 0x12},
Package () {0x0006FFFF, 0x00, 0x00, 0x13},
Package () {0x0007FFFF, 0x00, 0x00, 0x14},
Package () {0x0007FFFF, 0x01, 0x00, 0x15},
Package () {0x0007FFFF, 0x02, 0x00, 0x16},
Package () {0x0007FFFF, 0x03, 0x00, 0x17},
Package () {0x000DFFFF, 0x00, 0x00, 0x10},
Package () {0x000DFFFF, 0x01, 0x00, 0x11},
Package () {0x000DFFFF, 0x02, 0x00, 0x12},
Package () {0x0010FFFF, 0x00, 0x00, 0x13},
Package () {0x0010FFFF, 0x01, 0x00, 0x14},
Package () {0x0011FFFF, 0x00, 0x00, 0x18},
Package () {0x0012FFFF, 0x00, 0x00, 0x19},
Package () {0x0012FFFF, 0x01, 0x00, 0x1A},
Package () {0x0013FFFF, 0x00, 0x00, 0x1B},
Package () {0x0014FFFF, 0x00, 0x00, 0x15},
Package () {0x0015FFFF, 0x00, 0x00, 0x1C},
Package () {0x0015FFFF, 0x01, 0x00, 0x1D},
Package () {0x0015FFFF, 0x02, 0x00, 0x1E},
Package () {0x0015FFFF, 0x03, 0x00, 0x1F},
Package () {0x0016FFFF, 0x00, 0x00, 0x16},
Package () {0x0016FFFF, 0x01, 0x00, 0x17},
Package () {0x0016FFFF, 0x02, 0x00, 0x10},
Package () {0x0016FFFF, 0x03, 0x00, 0x11},
Package () {0x0017FFFF, 0x00, 0x00, 0x12},
Package () {0x0019FFFF, 0x00, 0x00, 0x20},
Package () {0x0019FFFF, 0x01, 0x00, 0x21},
Package () {0x0019FFFF, 0x02, 0x00, 0x22},
Package () {0x001CFFFF, 0x00, 0x00, 0x10},
Package () {0x001CFFFF, 0x01, 0x00, 0x11},
Package () {0x001CFFFF, 0x02, 0x00, 0x12},
Package () {0x001CFFFF, 0x03, 0x00, 0x13},
Package () {0x001DFFFF, 0x00, 0x00, 0x10},
Package () {0x001DFFFF, 0x01, 0x00, 0x11},
Package () {0x001DFFFF, 0x02, 0x00, 0x12},
Package () {0x001DFFFF, 0x03, 0x00, 0x13},
Package () {0x001EFFFF, 0x00, 0x00, 0x14},
Package () {0x001EFFFF, 0x01, 0x00, 0x15},
Package () {0x001EFFFF, 0x02, 0x00, 0x24},
Package () {0x001EFFFF, 0x03, 0x00, 0x25},
Package () {0x001FFFFF, 0x01, 0x00, 0x17},
Package () {0x001FFFFF, 0x02, 0x00, 0x14},
Package () {0x001FFFFF, 0x03, 0x00, 0x15},
Package () {0x001FFFFF, 0x00, 0x00, 0x16},
Else
Package () {0x0002FFFF, 0x00, 0x00, 0x0B},
Package () {0x0004FFFF, 0x00, 0x00, 0x0A},
Package () {0x0005FFFF, 0x00, 0x00, 0x0B},
Package () {0x0006FFFF, 0x00, 0x00, 0x0B},
Package () {0x0007FFFF, 0x00, 0x00, 0x0B},
Package () {0x0007FFFF, 0x01, 0x00, 0x0B},
Package () {0x0007FFFF, 0x02, 0x00, 0x0B},
Package () {0x0007FFFF, 0x03, 0x00, 0x0B},
Package () {0x000DFFFF, 0x00, 0x00, 0x0B},
Package () {0x000DFFFF, 0x01, 0x00, 0x0A},
Package () {0x000DFFFF, 0x02, 0x00, 0x0B},
Package () {0x0010FFFF, 0x00, 0x00, 0x0B},
Package () {0x0010FFFF, 0x01, 0x00, 0x0B},
Package () {0x0014FFFF, 0x00, 0x00, 0x0B},
Package () {0x0016FFFF, 0x00, 0x00, 0x0B},
Package () {0x0016FFFF, 0x01, 0x00, 0x0B},
Package () {0x0016FFFF, 0x02, 0x00, 0x0B},
Package () {0x0016FFFF, 0x03, 0x00, 0x0A},
Package () {0x0017FFFF, 0x00, 0x00, 0x0B},
Package () {0x001CFFFF, 0x00, 0x00, 0x0B},
Package () {0x001CFFFF, 0x01, 0x00, 0x0A},
Package () {0x001CFFFF, 0x02, 0x00, 0x0B},
Package () {0x001CFFFF, 0x03, 0x00, 0x0B},
Package () {0x001DFFFF, 0x00, 0x00, 0x0B},
Package () {0x001DFFFF, 0x01, 0x00, 0x0A},
Package () {0x001DFFFF, 0x02, 0x00, 0x0B},
Package () {0x001DFFFF, 0x03, 0x00, 0x0B},
Package () {0x001EFFFF, 0x00, 0x00, 0x0B},
Package () {0x001EFFFF, 0x01, 0x00, 0x0B},
Package () {0x001FFFFF, 0x01, 0x00, 0x0B},
Package () {0x001FFFFF, 0x02, 0x00, 0x0B},
Package () {0x001FFFFF, 0x03, 0x00, 0x0B},
Package () {0x001FFFFF, 0x00, 0x00, 0x0B},
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ieb241f2b91af52a7e2d0efe997d35732882ac463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49409
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 4ec163b..568bb6e 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -56,6 +56,7 @@
select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
+ select SOC_INTEL_COMMON_BLOCK_IRQ
select SOC_INTEL_COMMON_BLOCK_MEMINIT
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
select SOC_INTEL_COMMON_BLOCK_SA
diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
deleted file mode 100644
index 5bb30f0..0000000
--- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl
+++ /dev/null
@@ -1,159 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-Name (PICP, Package () {
- /* D31 */
- Package(){0x001FFFFF, 0, 0, 16 },
- /* D30 */
- Package(){0x001EFFFF, 0, 0, 16 },
- Package(){0x001EFFFF, 1, 0, 17 },
- Package(){0x001EFFFF, 2, 0, 36 },
- Package(){0x001EFFFF, 3, 0, 37 },
- /* D29 */
- Package(){0x001DFFFF, 0, 0, 16 },
- Package(){0x001DFFFF, 1, 0, 17 },
- Package(){0x001DFFFF, 2, 0, 18 },
- Package(){0x001DFFFF, 3, 0, 19 },
- /* D28 */
- Package(){0x001CFFFF, 0, 0, 16 },
- Package(){0x001CFFFF, 1, 0, 17 },
- Package(){0x001CFFFF, 2, 0, 18 },
- Package(){0x001CFFFF, 3, 0, 19 },
- /* D25 */
- Package(){0x0019FFFF, 0, 0, 31 },
- Package(){0x0019FFFF, 1, 0, 32 },
- Package(){0x0019FFFF, 2, 0, 33 },
- /* D23 */
- Package(){0x0017FFFF, 0, 0, 16 },
- /* D22 */
- Package(){0x0016FFFF, 0, 0, 16 },
- Package(){0x0016FFFF, 1, 0, 17 },
- Package(){0x0016FFFF, 2, 0, 18 },
- Package(){0x0016FFFF, 3, 0, 19 },
- /* D21 */
- Package(){0x0015FFFF, 0, 0, 27 },
- Package(){0x0015FFFF, 1, 0, 40 },
- Package(){0x0015FFFF, 2, 0, 29 },
- Package(){0x0015FFFF, 3, 0, 30 },
- /* D20 */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- /* D19 */
- Package(){0x0013FFFF, 0, 0, 43 },
- Package(){0x0013FFFF, 1, 0, 24 },
- Package(){0x0013FFFF, 2, 0, 25 },
- Package(){0x0013FFFF, 3, 0, 38 },
- /* D18 */
- Package(){0x0012FFFF, 0, 0, 16 },
- Package(){0x0012FFFF, 1, 0, 34 },
- /* D17 */
- Package(){0x0011FFFF, 0, 0, 35 },
- Package(){0x0011FFFF, 1, 0, 20 },
- Package(){0x0011FFFF, 2, 0, 21 },
- Package(){0x0011FFFF, 3, 0, 42 },
- /* D16 */
- Package(){0x0010FFFF, 0, 0, 23 },
- Package(){0x0010FFFF, 1, 0, 22 },
- Package(){0x0010FFFF, 3, 0, 19 },
- /* D13 */
- Package(){0x000DFFFF, 0, 0, 16 },
- Package(){0x000DFFFF, 1, 0, 17 },
- /* D8 */
- Package(){0x0008FFFF, 0, 0, 16 },
- /* D7 */
- Package(){0x0007FFFF, 0, 0, 16 },
- Package(){0x0007FFFF, 1, 0, 17 },
- Package(){0x0007FFFF, 2, 0, 18 },
- Package(){0x0007FFFF, 3, 0, 19 },
- /* D6 */
- Package(){0x0006FFFF, 0, 0, 16 },
- /* D5 */
- Package(){0x0005FFFF, 0, 0, 16 },
- /* D4 */
- Package(){0x0004FFFF, 0, 0, 16 },
- /* D2 */
- Package(){0x0002FFFF, 0, 0, 16 },
-})
-
-Name (PICN, Package () {
- /* D31 */
- Package(){0x001FFFFF, 0, 0, 11 },
- /* D30 */
- Package(){0x001EFFFF, 0, 0, 11 },
- Package(){0x001EFFFF, 1, 0, 10 },
- Package(){0x001EFFFF, 2, 0, 11 },
- Package(){0x001EFFFF, 3, 0, 11 },
- /* D29 */
- Package(){0x001DFFFF, 0, 0, 11 },
- Package(){0x001DFFFF, 1, 0, 10 },
- Package(){0x001DFFFF, 2, 0, 11 },
- Package(){0x001DFFFF, 3, 0, 11 },
- /* D28 */
- Package(){0x001CFFFF, 0, 0, 11 },
- Package(){0x001CFFFF, 1, 0, 10 },
- Package(){0x001CFFFF, 2, 0, 11 },
- Package(){0x001CFFFF, 3, 0, 11 },
- /* D25 */
- Package(){0x0019FFFF, 0, 0, 11 },
- Package(){0x0019FFFF, 1, 0, 10 },
- Package(){0x0019FFFF, 2, 0, 11 },
- /* D23 */
- Package(){0x0017FFFF, 0, 0, 11 },
- /* D22 */
- Package(){0x0016FFFF, 0, 0, 11 },
- Package(){0x0016FFFF, 1, 0, 10 },
- Package(){0x0016FFFF, 2, 0, 11 },
- Package(){0x0016FFFF, 3, 0, 11 },
- /* D21 */
- Package(){0x0015FFFF, 0, 0, 11 },
- Package(){0x0015FFFF, 1, 0, 10 },
- Package(){0x0015FFFF, 2, 0, 11 },
- Package(){0x0015FFFF, 3, 0, 11 },
- /* D20 */
- Package(){0x0014FFFF, 0, 0, 11 },
- Package(){0x0014FFFF, 0, 0, 10 },
- /* D19 */
- Package(){0x0013FFFF, 0, 0, 11 },
- Package(){0x0013FFFF, 1, 0, 10 },
- Package(){0x0013FFFF, 2, 0, 11 },
- Package(){0x0013FFFF, 3, 0, 11 },
- /* D18 */
- Package(){0x0012FFFF, 0, 0, 11 },
- Package(){0x0012FFFF, 1, 0, 10 },,
- /* D18 */
- Package(){0x0011FFFF, 0, 0, 11 },
- Package(){0x0011FFFF, 1, 0, 10 },
- Package(){0x0011FFFF, 2, 0, 11 },
- Package(){0x0011FFFF, 3, 0, 11 },
- /* D16 */
- Package(){0x0010FFFF, 0, 0, 11 },
- Package(){0x0010FFFF, 1, 0, 10 },
- Package(){0x0010FFFF, 2, 0, 11 },
- Package(){0x0010FFFF, 3, 0, 11 },
- /* D13 */
- Package(){0x000DFFFF, 0, 0, 11 },
- Package(){0x000DFFFF, 1, 0, 10 },
- /* D8 */
- Package(){0x0008FFFF, 0, 0, 11 },
- /* D7 */
- Package(){0x0007FFFF, 0, 0, 11 },
- Package(){0x0007FFFF, 1, 0, 10 },
- Package(){0x0007FFFF, 2, 0, 11 },
- Package(){0x0007FFFF, 3, 0, 11 },
- /* D6 */
- Package(){0x0006FFFF, 0, 0, 11 },
- /* D5 */
- Package(){0x0005FFFF, 0, 0, 11 },
- /* D4 */
- Package(){0x0004FFFF, 0, 0, 11 },
- /* D2 */
- Package(){0x0002FFFF, 0, 0, 11 },
-})
-
-Method (_PRT)
-{
- If (PICM) {
- Return (^PICP)
- } Else {
- Return (^PICN)
- }
-}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 3a53f2c..59bcf74 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -5,9 +5,6 @@
#include <soc/itss.h>
#include <soc/pcr_ids.h>
-/* PCI IRQ assignment */
-#include "pci_irqs.asl"
-
/* PCR access */
#include <soc/intel/common/acpi/pcr.asl>
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index eefc408..fd86582c 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -7,6 +7,7 @@
#include <intelblocks/acpi.h>
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
+#include <intelblocks/irq.h>
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
@@ -137,6 +138,19 @@
pcie_rp_update_devicetree(pch_lp_rp_groups);
}
+static void cpu_fill_ssdt(const struct device *dev)
+{
+ if (!generate_pin_irq_map())
+ printk(BIOS_ERR, "ERROR: Failed to generate ACPI _PRT table!\n");
+
+ generate_cpu_entries(dev);
+}
+
+static void cpu_set_north_irqs(struct device *dev)
+{
+ irq_program_non_pch();
+}
+
static struct device_operations pci_domain_ops = {
.read_resources = &pci_domain_read_resources,
.set_resources = &pci_domain_set_resources,
@@ -149,8 +163,9 @@
static struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
+ .enable_resources = cpu_set_north_irqs,
#if CONFIG(HAVE_ACPI_TABLES)
- .acpi_fill_ssdt = generate_cpu_entries,
+ .acpi_fill_ssdt = cpu_fill_ssdt,
#endif
};
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 7efcfab..63332fe 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -11,6 +11,7 @@
#include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h>
#include <intelblocks/cse.h>
+#include <intelblocks/irq.h>
#include <intelblocks/lpss.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/pmclib.h>
@@ -131,18 +132,211 @@
params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
}
+/*
+ * The FSP expects a certain list of PCI devices to be in the DevIntConfig table,
+ * regardless of whether or not they are used by the mainboard.
+ */
+static const struct slot_irq_constraints irq_constraints[] = {
+ {
+ .slot = SA_DEV_SLOT_IGD,
+ .fns = {
+ ANY_PIRQ(SA_DEVFN_IGD),
+ },
+ },
+ {
+ .slot = SA_DEV_SLOT_DPTF,
+ .fns = {
+ ANY_PIRQ(SA_DEVFN_DPTF),
+ },
+ },
+ {
+ .slot = SA_DEV_SLOT_IPU,
+ .fns = {
+ ANY_PIRQ(SA_DEVFN_IPU),
+ },
+ },
+ {
+ .slot = SA_DEV_SLOT_CPU_PCIE,
+ .fns = {
+ ANY_PIRQ(SA_DEVFN_CPU_PCIE),
+ },
+ },
+ {
+ .slot = SA_DEV_SLOT_TBT,
+ .fns = {
+ FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT0, PCI_INT_A),
+ FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT1, PCI_INT_B),
+ FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT2, PCI_INT_C),
+ FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT3, PCI_INT_D),
+ },
+ },
+ {
+ .slot = SA_DEV_SLOT_TCSS,
+ .fns = {
+ ANY_PIRQ(SA_DEVFN_TCSS_XHCI),
+ ANY_PIRQ(SA_DEVFN_TCSS_DMA0),
+ ANY_PIRQ(SA_DEVFN_TCSS_DMA1),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_SIO0,
+ .fns = {
+ ANY_PIRQ(PCH_DEVFN_THC0),
+ ANY_PIRQ(PCH_DEVFN_THC1),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_SIO1,
+ .fns = {
+ DIRECT_IRQ(PCH_DEVFN_UART3),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_ISH,
+ .fns = {
+ DIRECT_IRQ(PCH_DEVFN_ISH),
+ DIRECT_IRQ(PCH_DEVFN_GSPI2),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_SIO2,
+ .fns = {
+ DIRECT_IRQ(PCH_DEVFN_GSPI3),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_XHCI,
+ .fns = {
+ ANY_PIRQ(PCH_DEVFN_XHCI),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_SIO3,
+ .fns = {
+ DIRECT_IRQ(PCH_DEVFN_I2C0),
+ DIRECT_IRQ(PCH_DEVFN_I2C1),
+ DIRECT_IRQ(PCH_DEVFN_I2C2),
+ DIRECT_IRQ(PCH_DEVFN_I2C3),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_CSE,
+ .fns = {
+ ANY_PIRQ(PCH_DEVFN_CSE),
+ ANY_PIRQ(PCH_DEVFN_CSE_2),
+ ANY_PIRQ(PCH_DEVFN_CSE_IDER),
+ ANY_PIRQ(PCH_DEVFN_CSE_KT),
+ ANY_PIRQ(PCH_DEVFN_CSE_3),
+ ANY_PIRQ(PCH_DEVFN_CSE_4),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_SATA,
+ .fns = {
+ ANY_PIRQ(PCH_DEVFN_SATA),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_SIO4,
+ .fns = {
+ DIRECT_IRQ(PCH_DEVFN_I2C4),
+ DIRECT_IRQ(PCH_DEVFN_I2C5),
+ DIRECT_IRQ(PCH_DEVFN_UART2),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_PCIE,
+ .fns = {
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A),
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_PCIE_1,
+ .fns = {
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A),
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
+ FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_SIO5,
+ .fns = {
+ FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A),
+ FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B),
+ DIRECT_IRQ(PCH_DEVFN_GSPI0),
+ DIRECT_IRQ(PCH_DEVFN_GSPI1),
+ },
+ },
+ {
+ .slot = PCH_DEV_SLOT_ESPI,
+ .fns = {
+ ANY_PIRQ(PCH_DEVFN_HDA),
+ ANY_PIRQ(PCH_DEVFN_SMBUS),
+ ANY_PIRQ(PCH_DEVFN_GBE),
+ FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A),
+ },
+ },
+};
+
__weak void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config)
{
/* Override settings per board. */
}
+static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
+{
+ const struct pci_irq_entry *entry = get_cached_pci_irqs();
+ SI_PCH_DEVICE_INTERRUPT_CONFIG *config;
+ size_t pch_total = 0;
+ size_t cfg_count = 0;
+
+ if (!entry)
+ return NULL;
+
+ /* Count PCH devices */
+ while (entry) {
+ if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT)
+ ++pch_total;
+ entry = entry->next;
+ }
+
+ /* Convert PCH device entries to FSP format */
+ config = calloc(pch_total, sizeof(*config));
+ entry = get_cached_pci_irqs();
+ while (entry) {
+ if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) {
+ entry = entry->next;
+ continue;
+ }
+
+ config[cfg_count].Device = PCI_SLOT(entry->devfn);
+ config[cfg_count].Function = PCI_FUNC(entry->devfn);
+ config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin;
+ config[cfg_count].Irq = entry->irq;
+ ++cfg_count;
+
+ entry = entry->next;
+ }
+
+ *out_count = cfg_count;
+
+ return config;
+}
+
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
int i;
uint32_t cpu_id;
FSP_S_CONFIG *params = &supd->FspsConfig;
-
struct device *dev;
struct soc_intel_tigerlake_config *config;
config = config_of_soc();
@@ -175,6 +369,17 @@
/* Explicitly clear this field to avoid using defaults */
memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg));
+
+ /* Assign PCI IRQs */
+ if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints)))
+ die("ERROR: Unable to assign PCI IRQs, and no ACPI _PRT table is defined\n");
+
+ size_t pch_count = 0;
+ const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count);
+ params->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
+ params->NumOfDevIntConfig = pch_count;
+ printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
+
/*
* Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will
* evaluate this UPD value and skip sending command. There will be no
diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h
index f95f9f6..ad70290 100644
--- a/src/soc/intel/tigerlake/include/soc/irq.h
+++ b/src/soc/intel/tigerlake/include/soc/irq.h
@@ -9,8 +9,4 @@
#define PCH_IRQ10 10
#define PCH_IRQ11 11
-#define LPSS_UART0_IRQ 16
-#define LPSS_UART1_IRQ 17
-#define LPSS_UART2_IRQ 33
-
#endif /* _SOC_IRQ_H_ */
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index af1453b..297ca1f 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -73,6 +73,7 @@
#define SA_DEV_VMD PCI_DEV(0, SA_DEV_SLOT_VMD, 0)
/* PCH Devices */
+#define MIN_PCH_SLOT PCH_DEV_SLOT_SIO0
#define PCH_DEV_SLOT_SIO0 0x10
#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6)
#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7)