New mechanism to define SRAM/memory map with automatic bounds checking
This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.
The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).
BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.
Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>
diff --git a/src/mainboard/cubietech/cubieboard/Makefile.inc b/src/mainboard/cubietech/cubieboard/Makefile.inc
index 9bd0173..f3a6de2 100644
--- a/src/mainboard/cubietech/cubieboard/Makefile.inc
+++ b/src/mainboard/cubietech/cubieboard/Makefile.inc
@@ -1,2 +1,6 @@
bootblock-y += bootblock.c
romstage-y += romstage.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/cubietech/cubieboard/memlayout.ld b/src/mainboard/cubietech/cubieboard/memlayout.ld
new file mode 100644
index 0000000..ee3674d
--- /dev/null
+++ b/src/mainboard/cubietech/cubieboard/memlayout.ld
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+SECTIONS
+{
+ SRAM_START(0x0)
+ /* eGON.BT0: 32 bytes */
+ BOOTBLOCK(0x20, 0x5fa0)
+ STACK(0x6000, 8K)
+ SRAM_END(0x8000)
+
+ DRAM_START(0x40000000)
+ RAMSTAGE(0x40000000, 16M)
+ ROMSTAGE(0x41000000, 108K)
+}
+
diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig
index b275e88..c0e7095 100644
--- a/src/mainboard/emulation/qemu-armv7/Kconfig
+++ b/src/mainboard/emulation/qemu-armv7/Kconfig
@@ -49,45 +49,10 @@
string
default "ARM Ltd."
-config SYS_SDRAM_BASE
- hex "SDRAM base address"
- default 0x01000000
-
config DRAM_SIZE_MB
int
default 1024
-# Memory map for qemu vexpress-a9:
-#
-# 0x0000_0000: jump instruction (by qemu)
-# 0x0001_0000: bootblock (entry of kernel / firmware)
-# 0x0002_0000: romstage, assume up to 128KB in size.
-# 0x0007_ff00: stack pointer
-# 0x0010_0000: CBFS header
-# 0x0011_0000: CBFS data
-# 0x0100_0000: reserved for ramstage
-# 0x1000_0000: I/O map address
-#
-config STACK_TOP
- hex
- default 0x00100000
-
-config STACK_BOTTOM
- hex
- default 0x0007FF00
-
-config BOOTBLOCK_BASE
- hex
- default 0x00010000
-
-config ROMSTAGE_BASE
- hex
- default 0x00020000
-
-config RAMSTAGE_BASE
- hex
- default SYS_SDRAM_BASE
-
config BOOTBLOCK_ROM_OFFSET
hex
default 0x0
diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc
index 4119f932..d5742e1 100644
--- a/src/mainboard/emulation/qemu-armv7/Makefile.inc
+++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc
@@ -28,3 +28,7 @@
bootblock-y += mmio.c
romstage-y += mmio.c
ramstage-y += mmio.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c
index 84f88cf..af662c0 100644
--- a/src/mainboard/emulation/qemu-armv7/cbmem.c
+++ b/src/mainboard/emulation/qemu-armv7/cbmem.c
@@ -17,8 +17,9 @@
#include <stddef.h>
#include <cbmem.h>
+#include <symbols.h>
void *cbmem_top(void)
{
- return (void *)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20);
+ return _dram + (CONFIG_DRAM_SIZE_MB << 20);
}
diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c
index 1168881..c3760ab 100644
--- a/src/mainboard/emulation/qemu-armv7/media.c
+++ b/src/mainboard/emulation/qemu-armv7/media.c
@@ -14,6 +14,7 @@
*/
#include <cbfs.h>
#include <string.h>
+#include <symbols.h>
#include <console/console.h>
/* Simple memory-mapped ROM emulation. */
@@ -25,7 +26,7 @@
static void *emu_rom_map(struct cbfs_media *media, size_t offset, size_t count)
{
- return (void*)(offset + CONFIG_BOOTBLOCK_BASE);
+ return (void*)offset;
}
static void *emu_rom_unmap(struct cbfs_media *media, const void *address)
diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld
new file mode 100644
index 0000000..1485989
--- /dev/null
+++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * Memory map for qemu vexpress-a9:
+ *
+ * 0x0000_0000: jump instruction (by qemu)
+ * 0x0001_0000: bootblock (entry of kernel / firmware)
+ * 0x0002_0000: romstage, assume up to 128KB in size.
+ * 0x0007_ff00: stack pointer
+ * 0x0010_0000: CBFS header
+ * 0x0011_0000: CBFS data
+ * 0x0100_0000: reserved for ramstage
+ * 0x1000_0000: I/O map address
+ */
+
+SECTIONS
+{
+ /* TODO: does this thing emulate SRAM? */
+
+ BOOTBLOCK(0x10000, 64K)
+ ROMSTAGE(0x20000, 128K)
+ STACK(0x000FC000, 16K)
+
+ DRAM_START(0x01000000)
+ RAMSTAGE(0x01000000, 16M)
+}
diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig
index d7d5cc9..5425ca5 100644
--- a/src/mainboard/emulation/qemu-riscv/Kconfig
+++ b/src/mainboard/emulation/qemu-riscv/Kconfig
@@ -54,18 +54,6 @@
# 0x0011_0000: CBFS data
# 0x0100_0000: reserved for ramstage
-config BOOTBLOCK_BASE
- hex
- default 0x00000000
-
-config ROMSTAGE_BASE
- hex
- default 0x00020000
-
-config RAMSTAGE_BASE
- hex
- default 0x100000
-
config BOOTBLOCK_ROM_OFFSET
hex
default 0x0
@@ -82,16 +70,4 @@
hex
default 0x1000000
-config STACK_TOP
- hex
- default 0x0007ff00
-
-config STACK_BOTTOM
- hex
- default 0x00040000
-
-config STACK_SIZE
- hex
- default 0x0003ff00
-
endif # BOARD_EMULATION_QEMU_UCB_RISCV
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc
index bc01d2f..e60e0c1 100644
--- a/src/mainboard/emulation/qemu-riscv/Makefile.inc
+++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc
@@ -17,3 +17,7 @@
romstage-y += romstage.c
romstage-y += uart.c
ramstage-y += uart.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld
new file mode 100644
index 0000000..082ac8a2
--- /dev/null
+++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+SECTIONS
+{
+ DRAM_START(0x0)
+ BOOTBLOCK(0x0, 64K)
+ ROMSTAGE(0x20000, 128K)
+ STACK(0x40000, 0x3ff00)
+ PRERAM_CBMEM_CONSOLE(0x80000, 8K)
+ RAMSTAGE(0x100000, 16M)
+}
+
diff --git a/src/mainboard/google/daisy/Makefile.inc b/src/mainboard/google/daisy/Makefile.inc
index df9b797..1f041ab 100644
--- a/src/mainboard/google/daisy/Makefile.inc
+++ b/src/mainboard/google/daisy/Makefile.inc
@@ -26,3 +26,7 @@
ramstage-y += mainboard.c
ramstage-y += chromeos.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c
index 5840e51..138e498 100644
--- a/src/mainboard/google/daisy/mainboard.c
+++ b/src/mainboard/google/daisy/mainboard.c
@@ -36,20 +36,17 @@
#include <soc/samsung/exynos5250/dp.h>
#include <soc/samsung/exynos5250/periph.h>
#include <soc/samsung/exynos5250/usb.h>
+#include <symbols.h>
#include "exynos5250.h"
#define MMC0_GPIO_PIN (58)
/* convenient shorthand (in MB) */
-#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
+#define DRAM_START ((uintptr_t)_dram/MiB)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
-/* Arbitrary range of DMA memory for depthcharge's drivers */
-#define DMA_START (0x77300000)
-#define DMA_SIZE (0x00100000)
-
static struct edid edid = {
.ha = 1366,
.va = 768,
@@ -333,7 +330,8 @@
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
- mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
+ mmu_config_range((uintptr_t)_dma_coherent/MiB,
+ _dma_coherent_size/MiB, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
dcache_mmu_enable();
@@ -359,6 +357,6 @@
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
- dma->range_start = (intptr_t)DMA_START;
- dma->range_size = DMA_SIZE;
+ dma->range_start = (uintptr_t)_dma_coherent;
+ dma->range_size = _dma_coherent_size;
}
diff --git a/src/mainboard/google/daisy/memlayout.ld b/src/mainboard/google/daisy/memlayout.ld
new file mode 100644
index 0000000..72c018e
--- /dev/null
+++ b/src/mainboard/google/daisy/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/samsung/exynos5250/memlayout.ld>
diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
index 864e577..082985d 100644
--- a/src/mainboard/google/nyan/Kconfig
+++ b/src/mainboard/google/nyan/Kconfig
@@ -42,14 +42,6 @@
string
default "Nyan"
-config DRAM_DMA_START
- hex
- default 0x90000000
-
-config DRAM_DMA_SIZE
- hex
- default 0x00200000
-
choice
prompt "BCT boot media"
default NYAN_BCT_CFG_SPI
diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc
index 7ac11e8..6506aba 100644
--- a/src/mainboard/google/nyan/Makefile.inc
+++ b/src/mainboard/google/nyan/Makefile.inc
@@ -42,3 +42,7 @@
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
index b534ea9..e52db83 100644
--- a/src/mainboard/google/nyan/mainboard.c
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -30,6 +30,7 @@
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra/usb.h>
+#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@@ -268,6 +269,6 @@
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
- dma->range_start = CONFIG_DRAM_DMA_START;
- dma->range_size = CONFIG_DRAM_DMA_SIZE;
+ dma->range_start = (uintptr_t)_dma_coherent;
+ dma->range_size = _dma_coherent_size;
}
diff --git a/src/mainboard/google/nyan/memlayout.ld b/src/mainboard/google/nyan/memlayout.ld
new file mode 100644
index 0000000..33ce644
--- /dev/null
+++ b/src/mainboard/google/nyan/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/nvidia/tegra124/memlayout.ld>
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 1ff500b..f2077bb 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -39,6 +39,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/display.h>
+#include <symbols.h>
#include <timestamp.h>
static void __attribute__((noinline)) romstage(void)
@@ -52,24 +53,25 @@
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
- u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
- u32 dram_end = sdram_max_addressable_mb(); /* plus one... */
- u32 dram_size = dram_end - dram_start;
+ u32 dram_start_mb = (uintptr_t)_dram/MiB;
+ u32 dram_end_mb = sdram_max_addressable_mb();
+ u32 dram_size_mb = dram_end_mb - dram_start_mb;
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
- mmu_config_range(0, dram_start, DCACHE_OFF);
- /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
- mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
+ mmu_config_range(0, dram_start_mb, DCACHE_OFF);
+ /* SRAM is cached. MMU code will round size up to page size. */
+ mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
+ DCACHE_WRITEBACK);
/* DRAM is cached. */
- mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
+ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
- mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
- CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+ mmu_config_range((uintptr_t)_dma_coherent/MiB,
+ _dma_coherent_size/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
- if (dram_end < 4096)
- mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+ if (dram_end_mb < 4096)
+ mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();
diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig
index 2968b01..7334472 100644
--- a/src/mainboard/google/nyan_big/Kconfig
+++ b/src/mainboard/google/nyan_big/Kconfig
@@ -44,14 +44,6 @@
string
default "Nyan Big"
-config DRAM_DMA_START
- hex
- default 0x90000000
-
-config DRAM_DMA_SIZE
- hex
- default 0x00200000
-
choice
prompt "BCT boot media"
default NYAN_BIG_BCT_CFG_SPI
diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc
index 8ca495c..fddb44e 100644
--- a/src/mainboard/google/nyan_big/Makefile.inc
+++ b/src/mainboard/google/nyan_big/Makefile.inc
@@ -41,3 +41,7 @@
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c
index 86d9fe3..05f6fae 100644
--- a/src/mainboard/google/nyan_big/mainboard.c
+++ b/src/mainboard/google/nyan_big/mainboard.c
@@ -30,6 +30,7 @@
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra/usb.h>
+#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@@ -266,6 +267,6 @@
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
- dma->range_start = CONFIG_DRAM_DMA_START;
- dma->range_size = CONFIG_DRAM_DMA_SIZE;
+ dma->range_start = (uintptr_t)_dma_coherent;
+ dma->range_size = _dma_coherent_size;
}
diff --git a/src/mainboard/google/nyan_big/memlayout.ld b/src/mainboard/google/nyan_big/memlayout.ld
new file mode 100644
index 0000000..33ce644
--- /dev/null
+++ b/src/mainboard/google/nyan_big/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/nvidia/tegra124/memlayout.ld>
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index 1ff500b..f2077bb 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -39,6 +39,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/display.h>
+#include <symbols.h>
#include <timestamp.h>
static void __attribute__((noinline)) romstage(void)
@@ -52,24 +53,25 @@
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
- u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
- u32 dram_end = sdram_max_addressable_mb(); /* plus one... */
- u32 dram_size = dram_end - dram_start;
+ u32 dram_start_mb = (uintptr_t)_dram/MiB;
+ u32 dram_end_mb = sdram_max_addressable_mb();
+ u32 dram_size_mb = dram_end_mb - dram_start_mb;
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
- mmu_config_range(0, dram_start, DCACHE_OFF);
- /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
- mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
+ mmu_config_range(0, dram_start_mb, DCACHE_OFF);
+ /* SRAM is cached. MMU code will round size up to page size. */
+ mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
+ DCACHE_WRITEBACK);
/* DRAM is cached. */
- mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
+ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
- mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
- CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+ mmu_config_range((uintptr_t)_dma_coherent/MiB,
+ _dma_coherent_size/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
- if (dram_end < 4096)
- mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+ if (dram_end_mb < 4096)
+ mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();
diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig
index 5938e7e..3495919 100644
--- a/src/mainboard/google/nyan_blaze/Kconfig
+++ b/src/mainboard/google/nyan_blaze/Kconfig
@@ -45,14 +45,6 @@
string
default "Nyan Blaze"
-config DRAM_DMA_START
- hex
- default 0x90000000
-
-config DRAM_DMA_SIZE
- hex
- default 0x00200000
-
choice
prompt "BCT boot media"
default NYAN_BLAZE_BCT_CFG_SPI
diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc
index dc998d1..3430409 100644
--- a/src/mainboard/google/nyan_blaze/Makefile.inc
+++ b/src/mainboard/google/nyan_blaze/Makefile.inc
@@ -45,3 +45,8 @@
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+bootblock-y += memlayout.ld
+verstage-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c
index ccbaf63..5f1cb49 100644
--- a/src/mainboard/google/nyan_blaze/mainboard.c
+++ b/src/mainboard/google/nyan_blaze/mainboard.c
@@ -30,6 +30,7 @@
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra/usb.h>
+#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@@ -266,6 +267,6 @@
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
- dma->range_start = CONFIG_DRAM_DMA_START;
- dma->range_size = CONFIG_DRAM_DMA_SIZE;
+ dma->range_start = (uintptr_t)_dma_coherent;
+ dma->range_size = _dma_coherent_size;
}
diff --git a/src/mainboard/google/nyan_blaze/memlayout.ld b/src/mainboard/google/nyan_blaze/memlayout.ld
new file mode 100644
index 0000000..33ce644
--- /dev/null
+++ b/src/mainboard/google/nyan_blaze/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/nvidia/tegra124/memlayout.ld>
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index fca705d..fb1b9e2 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -39,6 +39,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/display.h>
+#include <symbols.h>
#include <timestamp.h>
static void __attribute__((noinline)) romstage(void)
@@ -52,29 +53,30 @@
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
- u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
- u32 dram_end = sdram_max_addressable_mb(); /* plus one... */
- u32 dram_size = dram_end - dram_start;
+ u32 dram_start_mb = (uintptr_t)_dram/MiB;
+ u32 dram_end_mb = sdram_max_addressable_mb();
+ u32 dram_size_mb = dram_end_mb - dram_start_mb;
#if !CONFIG_VBOOT2_VERIFY_FIRMWARE
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
- mmu_config_range(0, dram_start, DCACHE_OFF);
- /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
- mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
+ mmu_config_range(0, dram_start_mb, DCACHE_OFF);
+ /* SRAM is cached. MMU code will round size up to page size. */
+ mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
+ DCACHE_WRITEBACK);
/* The space above DRAM is uncached. */
- if (dram_end < 4096)
- mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+ if (dram_end_mb < 4096)
+ mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();
#endif
/* DRAM is cached. */
- mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
+ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
- mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
- CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+ mmu_config_range((uintptr_t)_dma_coherent/MiB,
+ _dma_coherent_size/MiB, DCACHE_OFF);
/*
* A watchdog reset only resets part of the system so it ends up in
diff --git a/src/mainboard/google/peach_pit/Makefile.inc b/src/mainboard/google/peach_pit/Makefile.inc
index df9b797..1f041ab 100644
--- a/src/mainboard/google/peach_pit/Makefile.inc
+++ b/src/mainboard/google/peach_pit/Makefile.inc
@@ -26,3 +26,7 @@
ramstage-y += mainboard.c
ramstage-y += chromeos.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c
index 1a15bd2..b6f49e2 100644
--- a/src/mainboard/google/peach_pit/mainboard.c
+++ b/src/mainboard/google/peach_pit/mainboard.c
@@ -40,15 +40,12 @@
#include <drivers/parade/ps8625/ps8625.h>
#include <ec/google/chromeec/ec.h>
#include <stdlib.h>
+#include <symbols.h>
/* convenient shorthand (in MB) */
-#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
+#define DRAM_START ((uintptr_t)_dram/MiB)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
-/* Arbitrary range of DMA memory for depthcharge's drivers */
-#define DMA_START (0x77300000)
-#define DMA_SIZE (0x00100000)
-
static struct edid edid = {
.ha = 1366,
.va = 768,
@@ -469,7 +466,8 @@
/* set up caching for the DRAM */
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
- mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
+ mmu_config_range((uintptr_t)_dma_coherent/MiB,
+ _dma_coherent_size/MiB, DCACHE_OFF);
const unsigned epll_hz = 192000000;
const unsigned sample_rate = 48000;
@@ -493,6 +491,6 @@
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
- dma->range_start = (intptr_t)DMA_START;
- dma->range_size = DMA_SIZE;
+ dma->range_start = (uintptr_t)_dma_coherent;
+ dma->range_size = _dma_coherent_size;
}
diff --git a/src/mainboard/google/peach_pit/memlayout.ld b/src/mainboard/google/peach_pit/memlayout.ld
new file mode 100644
index 0000000..565ba89
--- /dev/null
+++ b/src/mainboard/google/peach_pit/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/samsung/exynos5420/memlayout.ld>
diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index 2a1ce99..e41745f 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -40,3 +40,7 @@
ramstage-y += mainboard.c
ramstage-y += reset.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld
new file mode 100644
index 0000000..b9def51
--- /dev/null
+++ b/src/mainboard/google/rush/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/nvidia/tegra132/memlayout.ld>
diff --git a/src/mainboard/google/rush_ryu/Makefile.inc b/src/mainboard/google/rush_ryu/Makefile.inc
index 2fe12a4..67a3fac 100644
--- a/src/mainboard/google/rush_ryu/Makefile.inc
+++ b/src/mainboard/google/rush_ryu/Makefile.inc
@@ -41,3 +41,7 @@
ramstage-y += mainboard.c
ramstage-y += reset.c
ramstage-y += chromeos.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld
new file mode 100644
index 0000000..b9def51
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/nvidia/tegra132/memlayout.ld>
diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig
index b0c064c..3e1e016 100644
--- a/src/mainboard/google/storm/Kconfig
+++ b/src/mainboard/google/storm/Kconfig
@@ -48,12 +48,4 @@
default 512 if BOARD_VARIANT_AP148
default 1024
-config DRAM_DMA_START
- hex
- default 0x5a000000
-
-config DRAM_DMA_SIZE
- hex
- default 0x00200000
-
endif # BOARD_GOOGLE_STORM
diff --git a/src/mainboard/google/storm/Makefile.inc b/src/mainboard/google/storm/Makefile.inc
index 907638a..6ee0841 100644
--- a/src/mainboard/google/storm/Makefile.inc
+++ b/src/mainboard/google/storm/Makefile.inc
@@ -25,3 +25,7 @@
ramstage-y += boardid.c
ramstage-y += cdp.c
ramstage-y += mainboard.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c
index 3da6f90..478e2a8 100644
--- a/src/mainboard/google/storm/mainboard.c
+++ b/src/mainboard/google/storm/mainboard.c
@@ -25,19 +25,20 @@
#include <device/device.h>
#include <gpiolib.h>
#include <string.h>
+#include <symbols.h>
#include <soc/qualcomm/ipq806x/include/clock.h>
#include <soc/qualcomm/ipq806x/include/gpio.h>
#include <soc/qualcomm/ipq806x/include/usb.h>
/* convenient shorthand (in MB) */
-#define DRAM_START (CONFIG_SYS_SDRAM_BASE / MiB)
+#define DRAM_START ((uintptr_t)_dram / MiB)
#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB)
#define DRAM_END (DRAM_START + DRAM_SIZE)
/* DMA memory for drivers */
-#define DMA_START (CONFIG_DRAM_DMA_START / MiB)
-#define DMA_SIZE (CONFIG_DRAM_DMA_SIZE / MiB)
+#define DMA_START ((uintptr_t)_dma_coherent / MiB)
+#define DMA_SIZE (_dma_coherent_size / MiB)
#define USB_ENABLE_GPIO 51
@@ -134,8 +135,8 @@
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
- dma->range_start = CONFIG_DRAM_DMA_START;
- dma->range_size = CONFIG_DRAM_DMA_SIZE;
+ dma->range_start = (uintptr_t)_dma_coherent;
+ dma->range_size = _dma_coherent_size;
}
static int read_gpio(gpio_t gpio_num)
diff --git a/src/mainboard/google/storm/memlayout.ld b/src/mainboard/google/storm/memlayout.ld
new file mode 100644
index 0000000..1735835
--- /dev/null
+++ b/src/mainboard/google/storm/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/qualcomm/ipq806x/memlayout.ld>
diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig
index bde26d6..a9363f9 100644
--- a/src/mainboard/google/urara/Kconfig
+++ b/src/mainboard/google/urara/Kconfig
@@ -38,10 +38,6 @@
string
default "ImgTec Pistachio Virtual Platform"
-config SYS_SDRAM_BASE
- hex "SDRAM base address"
- default 0x80000000
-
config DRAM_SIZE_MB
int
default 256
diff --git a/src/mainboard/google/urara/Makefile.inc b/src/mainboard/google/urara/Makefile.inc
index 4ce6398..5a9dc02 100644
--- a/src/mainboard/google/urara/Makefile.inc
+++ b/src/mainboard/google/urara/Makefile.inc
@@ -21,3 +21,6 @@
ramstage-y += mainboard.c
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/urara/memlayout.ld b/src/mainboard/google/urara/memlayout.ld
new file mode 100644
index 0000000..ab0b4dd
--- /dev/null
+++ b/src/mainboard/google/urara/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/imgtec/pistachio/memlayout.ld>
diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig
index 97a0097..7c4f084 100644
--- a/src/mainboard/google/veyron_pinky/Kconfig
+++ b/src/mainboard/google/veyron_pinky/Kconfig
@@ -61,14 +61,6 @@
int
default 2
-config DRAM_DMA_START
- hex
- default 0x10000000
-
-config DRAM_DMA_SIZE
- hex
- default 0x00200000
-
config DRAM_SIZE_MB
int
default 2048
diff --git a/src/mainboard/google/veyron_pinky/Makefile.inc b/src/mainboard/google/veyron_pinky/Makefile.inc
index c33cfa3..0cc89d0 100644
--- a/src/mainboard/google/veyron_pinky/Makefile.inc
+++ b/src/mainboard/google/veyron_pinky/Makefile.inc
@@ -35,3 +35,8 @@
ramstage-y += chromeos.c
ramstage-y += mainboard.c
ramstage-y += reset.c
+
+bootblock-y += memlayout.ld
+verstage-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
index 232010d..19d6675 100644
--- a/src/mainboard/google/veyron_pinky/mainboard.c
+++ b/src/mainboard/google/veyron_pinky/mainboard.c
@@ -22,6 +22,7 @@
#include <arch/cache.h>
#include <delay.h>
#include <edid.h>
+#include <symbols.h>
#include <vbe.h>
#include <boot/coreboot_tables.h>
#include <device/i2c.h>
@@ -153,6 +154,6 @@
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
- dma->range_start = CONFIG_DRAM_DMA_START;
- dma->range_size = CONFIG_DRAM_DMA_SIZE;
+ dma->range_start = (uintptr_t)_dma_coherent;
+ dma->range_size = _dma_coherent_size;
}
diff --git a/src/mainboard/google/veyron_pinky/memlayout.ld b/src/mainboard/google/veyron_pinky/memlayout.ld
new file mode 100644
index 0000000..a8b7465
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/rockchip/rk3288/memlayout.ld>
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c
index f972ee2..1d7812b 100644
--- a/src/mainboard/google/veyron_pinky/romstage.c
+++ b/src/mainboard/google/veyron_pinky/romstage.c
@@ -35,6 +35,7 @@
#include <soc/rockchip/rk3288/clock.h>
#include <soc/rockchip/rk3288/pwm.h>
#include <soc/rockchip/rk3288/grf.h>
+#include <symbols.h>
#include "timer.h"
static void regulate_vdd_log(unsigned int mv)
@@ -64,9 +65,9 @@
start_romstage_time = timestamp_get();
#endif
/* used for MMU and CBMEM setup, in MB */
- u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
- u32 dram_size = CONFIG_DRAM_SIZE_MB;
- u32 dram_end = dram_start + dram_size;
+ u32 dram_start_mb = (uintptr_t)_dram/MiB;
+ u32 dram_size_mb = CONFIG_DRAM_SIZE_MB;
+ u32 dram_end_mb = dram_start_mb + dram_size_mb;
console_init();
@@ -81,15 +82,15 @@
#endif
mmu_init();
/* Device memory below DRAM is uncached. */
- mmu_config_range(0, dram_start, DCACHE_OFF);
+ mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* DRAM is cached. */
- mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
+ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
- mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
- CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+ mmu_config_range((uintptr_t)_dma_coherent/MiB,
+ _dma_coherent_size/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
- if (dram_end < 4096)
- mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+ if (dram_end_mb < 4096)
+ mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
dcache_mmu_enable();
cbmem_initialize_empty();
diff --git a/src/mainboard/ti/beaglebone/Makefile.inc b/src/mainboard/ti/beaglebone/Makefile.inc
index 71d749d..1a2143f 100644
--- a/src/mainboard/ti/beaglebone/Makefile.inc
+++ b/src/mainboard/ti/beaglebone/Makefile.inc
@@ -21,3 +21,7 @@
romstage-y += romstage.c
#ramstage-y += ramstage.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/ti/beaglebone/memlayout.ld b/src/mainboard/ti/beaglebone/memlayout.ld
new file mode 100644
index 0000000..ff79e70
--- /dev/null
+++ b/src/mainboard/ti/beaglebone/memlayout.ld
@@ -0,0 +1 @@
+#include <cpu/ti/am335x/memlayout.ld>