soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack
descriptors impacting the way of coreboot's creation of domains.
Separates the codes as preparation for 6th Gen and later platforms.
Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81312
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c
index cdf9834..ecfc1f7 100644
--- a/src/soc/intel/xeon_sp/spr/ioat.c
+++ b/src/soc/intel/xeon_sp/spr/ioat.c
@@ -79,10 +79,10 @@
}
}
-void soc_create_ioat_domains(const union xeon_domain_path path,
- struct bus *const bus,
- const STACK_RES *const sr,
- const size_t pci_segment_group)
+void create_ioat_domains(const union xeon_domain_path path,
+ struct bus *const bus,
+ const STACK_RES *const sr,
+ const size_t pci_segment_group)
{
if (sr->BusLimit < sr->BusBase + HQM_BUS_OFFSET + HQM_RESERVED_BUS) {
printk(BIOS_WARNING,