diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 592c70f..b8df7aa 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -39,6 +39,7 @@
 #include <southbridge/intel/common/acpi_pirq_gen.h>
 #include <southbridge/intel/common/pmutil.h>
 #include <southbridge/intel/common/rtc.h>
+#include <southbridge/intel/common/spi.h>
 
 #define NMI_OFF	0
 
@@ -874,33 +875,7 @@
 
 static void lpc_final(struct device *dev)
 {
-	u16 spi_opprefix	= SPI_OPPREFIX;
-	u16 spi_optype		= SPI_OPTYPE;
-	u32 spi_opmenu[2]	= { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER };
-
-	/* Configure SPI opcode menu; devicetree may override defaults. */
-	const config_t *const config = dev->chip_info;
-	if (config && config->spi.ops[0].op) {
-		unsigned int i;
-
-		spi_opprefix	= 0;
-		spi_optype	= 0;
-		spi_opmenu[0]	= 0;
-		spi_opmenu[1]	= 0;
-		for (i = 0; i < sizeof(spi_opprefix); ++i)
-			spi_opprefix |= config->spi.opprefixes[i] << i * 8;
-		for (i = 0; i < sizeof(spi_opmenu); ++i) {
-			spi_optype |=
-				config->spi.ops[i].is_write << 2 * i |
-				config->spi.ops[i].needs_address << (2 * i + 1);
-			spi_opmenu[i / 4] |=
-				config->spi.ops[i].op << (i % 4) * 8;
-		}
-	}
-	RCBA16(0x3894) = spi_opprefix;
-	RCBA16(0x3896) = spi_optype;
-	RCBA32(0x3898) = spi_opmenu[0];
-	RCBA32(0x389c) = spi_opmenu[1];
+	spi_finalize_ops();
 
 	/* Call SMM finalize() handlers before resume */
 	if (CONFIG(HAVE_SMI_HANDLER)) {
@@ -911,6 +886,23 @@
 	}
 }
 
+void intel_southbridge_override_spi(
+		struct intel_swseq_spi_config *spi_config)
+{
+	struct device *dev = pcidev_on_root(0x1f, 0);
+
+	if (!dev)
+		return;
+	/* Devicetree may override defaults. */
+	const config_t *const config = dev->chip_info;
+
+	if (!config)
+		return;
+
+	if (config->spi.ops[0].op != 0)
+		memcpy(spi_config, &config->spi, sizeof(*spi_config));
+}
+
 static struct pci_operations pci_ops = {
 	.set_subsystem = pci_dev_set_subsystem,
 };