tree 24117bbce13331ada1476d3b5251df7973dab9a9
parent b21bc9d9dffd84886081462cd0555f201e023f4b
author Kilari Raasi <kilari.raasi@intel.com> 1699346114 +0530
committer Subrata Banik <subratabanik@google.com> 1702271178 +0000

soc/intel/meteorlake: Disable MarginLimitCheck and RMC UPDs

By default MarginLimitCheck and RMC UPDs are enabled in FSP
which enables fast and cold boot retraining causing the
boot time increase. So, disabling the same UPDs to fix it.

Change-Id: Ib15d37dbe177f31590f23de4e239a2e82abf1335
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>