diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 42cc7ce..093411f 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -17,15 +17,19 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-config NORTHBRIDGE_INTEL_I945GC
+config NORTHBRIDGE_INTEL_I945
 	bool
+
+if NORTHBRIDGE_INTEL_I945
+
+config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
+	def_bool y
 	select HAVE_DEBUG_RAM_SETUP
 
-config NORTHBRIDGE_INTEL_I945GM
-	bool
-	select HAVE_DEBUG_RAM_SETUP
-
-if NORTHBRIDGE_INTEL_I945GC || NORTHBRIDGE_INTEL_I945GM
+config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+	def_bool n
+config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
+	def_bool n
 
 config VGA_BIOS_ID
 	string
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 14c66c4..f27dca0 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -91,7 +91,7 @@
 		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
 	printk(BIOS_DEBUG, "\n");
-#if CONFIG_NORTHBRIDGE_INTEL_I945GC
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
 	printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
 #endif
 }
@@ -140,7 +140,7 @@
 		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
 	printk(BIOS_DEBUG, "\n");
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
 	printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
 #endif
 }
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index a4512d7..478a9c8 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -113,7 +113,7 @@
 static int memclk(void)
 {
 	int offset = 0;
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
 	offset++;
 #endif
 	switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
@@ -125,7 +125,7 @@
 	return -1;
 }
 
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
 static u16 fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
@@ -136,7 +136,7 @@
 	}
 	return 0xffff;
 }
-#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
+#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
 static u16 fsbclk(void)
 {
 	switch (MCHBAR32(CLKCFG) & 7) {
@@ -1075,7 +1075,7 @@
 	return nc;
 }
 
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
 /* Strength multiplier tables */
 static const u8 dual_channel_strength_multiplier[] = {
 	0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@@ -1130,7 +1130,7 @@
 	0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 	0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
 };
-#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
+#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
 static const u8 dual_channel_strength_multiplier[] = {
 	0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
 	0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@@ -2186,7 +2186,7 @@
 	/**
 	 * We add the indices according to our clocks from CLKCFG.
 	 */
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
 	static const u32 data_clock_crossing[] = {
 		0x00100401, 0x00000000, /* DDR400 FSB400 */
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2231,7 +2231,7 @@
 		0xffffffff, 0xffffffff, /*  nonexistant  */
 	};
 
-#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
+#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
 	/* i945 G/P */
 	static const u32 data_clock_crossing[] = {
 		0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2822,9 +2822,9 @@
 {
 	u8 clocks[2] = { 0, 0 };
 
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
 #define CLOCKS_WIDTH 2
-#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
+#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
 #define CLOCKS_WIDTH 3
 #endif
 	if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)