use seperate array for core 2 cpus (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 04d60dd..e252093 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -620,6 +620,85 @@
 		//{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
 	};
 
+	static const msr_entry_t model6fx_global_msrs[] = {
+		{ 0x0017, "IA32_PLATFORM_ID" },
+		{ 0x002a, "EBL_CR_POWERON" },
+		{ 0x003f, "IA32_TEMPERATURE_OFFSET" },
+		{ 0x00a8, "EMTTM_CR_TABLE0" },
+		{ 0x00a9, "EMTTM_CR_TABLE1" },
+		{ 0x00aa, "EMTTM_CR_TABLE2" },
+		{ 0x00ab, "EMTTM_CR_TABLE3" },
+		{ 0x00ac, "EMTTM_CR_TABLE4" },
+		{ 0x00ad, "EMTTM_CR_TABLE5" },
+		{ 0x00cd, "FSB_CLOCK_STS" },
+		{ 0x00e2, "PMG_CST_CONFIG_CONTROL" },
+		{ 0x00e3, "PMG_IO_BASE_ADDR" },
+		{ 0x00e4, "PMG_IO_CAPTURE_ADDR" },
+		{ 0x00ee, "EXT_CONFIG" },
+		{ 0x011e, "BBL_CR_CTL3" },
+		{ 0x0194, "CLOCK_FLEX_MAX" },
+		{ 0x0198, "IA32_PERF_STATUS" },
+		{ 0x01a0, "IA32_MISC_ENABLES" },
+		{ 0x01aa, "PIC_SENS_CFG" },
+		{ 0x0400, "IA32_MC0_CTL" },
+		{ 0x0401, "IA32_MC0_STATUS" },
+		{ 0x0402, "IA32_MC0_ADDR" },
+		//{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
+		{ 0x040c, "IA32_MC4_CTL" },
+		{ 0x040d, "IA32_MC4_STATUS" },
+		{ 0x040e, "IA32_MC4_ADDR" },
+		//{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
+	};
+
+	static const msr_entry_t model6fx_per_core_msrs[] = {
+		{ 0x0010, "IA32_TIME_STAMP_COUNTER" },
+		{ 0x001b, "IA32_APIC_BASE" },
+		{ 0x003a, "IA32_FEATURE_CONTROL" },
+		//{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
+		{ 0x008b, "IA32_BIOS_SIGN_ID" },
+		{ 0x00e1, "SMM_CST_MISC_INFO" },
+		{ 0x00e7, "IA32_MPERF" },
+		{ 0x00e8, "IA32_APERF" },
+		{ 0x00fe, "IA32_MTRRCAP" },
+		{ 0x0179, "IA32_MCG_CAP" },
+		{ 0x017a, "IA32_MCG_STATUS" },
+		{ 0x0199, "IA32_PERF_CONTROL" },
+		{ 0x019a, "IA32_THERM_CTL" },
+		{ 0x019b, "IA32_THERM_INTERRUPT" },
+		{ 0x019c, "IA32_THERM_STATUS" },
+		{ 0x019d, "MSR_THERM2_CTL" },
+		{ 0x01d9, "IA32_DEBUGCTL" },
+		{ 0x0200, "IA32_MTRR_PHYSBASE0" },
+		{ 0x0201, "IA32_MTRR_PHYSMASK0" },
+		{ 0x0202, "IA32_MTRR_PHYSBASE1" },
+		{ 0x0203, "IA32_MTRR_PHYSMASK1" },
+		{ 0x0204, "IA32_MTRR_PHYSBASE2" },
+		{ 0x0205, "IA32_MTRR_PHYSMASK2" },
+		{ 0x0206, "IA32_MTRR_PHYSBASE3" },
+		{ 0x0207, "IA32_MTRR_PHYSMASK3" },
+		{ 0x0208, "IA32_MTRR_PHYSBASE4" },
+		{ 0x0209, "IA32_MTRR_PHYSMASK4" },
+		{ 0x020a, "IA32_MTRR_PHYSBASE5" },
+		{ 0x020b, "IA32_MTRR_PHYSMASK5" },
+		{ 0x020c, "IA32_MTRR_PHYSBASE6" },
+		{ 0x020d, "IA32_MTRR_PHYSMASK6" },
+		{ 0x020e, "IA32_MTRR_PHYSBASE7" },
+		{ 0x020f, "IA32_MTRR_PHYSMASK7" },
+		{ 0x0250, "IA32_MTRR_FIX64K_00000" },
+		{ 0x0258, "IA32_MTRR_FIX16K_80000" },
+		{ 0x0259, "IA32_MTRR_FIX16K_A0000" },
+		{ 0x0268, "IA32_MTRR_FIX4K_C0000" },
+		{ 0x0269, "IA32_MTRR_FIX4K_C8000" },
+		{ 0x026a, "IA32_MTRR_FIX4K_D0000" },
+		{ 0x026b, "IA32_MTRR_FIX4K_D8000" },
+		{ 0x026c, "IA32_MTRR_FIX4K_E0000" },
+		{ 0x026d, "IA32_MTRR_FIX4K_E8000" },
+		{ 0x026e, "IA32_MTRR_FIX4K_F0000" },
+		{ 0x026f, "IA32_MTRR_FIX4K_F8000" },
+		{ 0x02ff, "IA32_MTRR_DEF_TYPE" },
+		//{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
+	};
+
 	typedef struct {
 		unsigned int model;
 		const msr_entry_t *global_msrs;
@@ -630,7 +709,7 @@
 
 	cpu_t cpulist[] = {
 		{ 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
-		{ 0x006f0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, // for now
+		{ 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
 	};
 
 	cpu_t *cpu = NULL;