build system: normalize linker script file names

We have .lb, .lds, and .ld in the tree. Go for .ld everywhere.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/arch/riscv/id.lds b/src/arch/riscv/id.ld
similarity index 100%
rename from src/arch/riscv/id.lds
rename to src/arch/riscv/id.ld
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 5d49abc..175a767 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -72,13 +72,13 @@
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
 
-bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb
-bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds
-bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds
-bootblock_lds += $(src)/arch/x86/lib/id.lds
+bootblock_lds = $(src)/arch/x86/init/ldscript_failover.ld
+bootblock_lds += $(src)/cpu/x86/16bit/entry16.ld
+bootblock_lds += $(src)/cpu/x86/16bit/reset16.ld
+bootblock_lds += $(src)/arch/x86/lib/id.ld
 bootblock_lds += $(chipset_bootblock_lds)
 ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
-bootblock_lds += $(src)/cpu/intel/fit/fit.lds
+bootblock_lds += $(src)/cpu/intel/fit/fit.ld
 endif
 
 bootblock_inc = $(src)/arch/x86/init/prologue.inc
@@ -141,7 +141,7 @@
 ldscripts =
 ldscripts += $(src)/arch/x86/init/romstage.ld
 crt0s += $(src)/cpu/x86/32bit/entry32.inc
-ldscripts += $(src)/cpu/x86/32bit/entry32.lds
+ldscripts += $(src)/cpu/x86/32bit/entry32.ld
 
 crt0s += $(src)/cpu/x86/fpu_enable.inc
 ifeq ($(CONFIG_SSE),y)
diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.ld
similarity index 100%
rename from src/arch/x86/init/ldscript_failover.lb
rename to src/arch/x86/init/ldscript_failover.ld
diff --git a/src/arch/x86/lib/id.lds b/src/arch/x86/lib/id.ld
similarity index 100%
rename from src/arch/x86/lib/id.lds
rename to src/arch/x86/lib/id.ld
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
index ff0b58c..c68bf9e 100644
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -25,7 +25,7 @@
 
 chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
 chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
-chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata.lds
-chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata_ex.lds
+chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata.ld
+chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata_ex.ld
 
 ROMCCFLAGS := -mcpu=i386 -O2
diff --git a/src/cpu/dmp/vortex86ex/biosdata.lds b/src/cpu/dmp/vortex86ex/biosdata.ld
similarity index 100%
rename from src/cpu/dmp/vortex86ex/biosdata.lds
rename to src/cpu/dmp/vortex86ex/biosdata.ld
diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.lds b/src/cpu/dmp/vortex86ex/biosdata_ex.ld
similarity index 100%
rename from src/cpu/dmp/vortex86ex/biosdata_ex.lds
rename to src/cpu/dmp/vortex86ex/biosdata_ex.ld
diff --git a/src/cpu/intel/fit/fit.lds b/src/cpu/intel/fit/fit.ld
similarity index 100%
rename from src/cpu/intel/fit/fit.lds
rename to src/cpu/intel/fit/fit.ld
diff --git a/src/cpu/x86/16bit/entry16.lds b/src/cpu/x86/16bit/entry16.ld
similarity index 100%
rename from src/cpu/x86/16bit/entry16.lds
rename to src/cpu/x86/16bit/entry16.ld
diff --git a/src/cpu/x86/16bit/reset16.lds b/src/cpu/x86/16bit/reset16.ld
similarity index 100%
rename from src/cpu/x86/16bit/reset16.lds
rename to src/cpu/x86/16bit/reset16.ld
diff --git a/src/cpu/x86/32bit/entry32.lds b/src/cpu/x86/32bit/entry32.ld
similarity index 100%
rename from src/cpu/x86/32bit/entry32.lds
rename to src/cpu/x86/32bit/entry32.ld
diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc
index 39ebdbd..1963880 100644
--- a/src/northbridge/via/vx800/Makefile.inc
+++ b/src/northbridge/via/vx800/Makefile.inc
@@ -24,4 +24,4 @@
 ramstage-y += ide.c
 
 chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc
-chipset_bootblock_lds += $(src)/northbridge/via/vx800/romstrap.lds
+chipset_bootblock_lds += $(src)/northbridge/via/vx800/romstrap.ld
diff --git a/src/northbridge/via/vx800/romstrap.lds b/src/northbridge/via/vx800/romstrap.ld
similarity index 100%
rename from src/northbridge/via/vx800/romstrap.lds
rename to src/northbridge/via/vx800/romstrap.ld
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 15fd859..85282dd 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -45,4 +45,4 @@
 
 
 chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
-chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.lds
+chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.ld
diff --git a/src/northbridge/via/vx900/romstrap.lds b/src/northbridge/via/vx900/romstrap.ld
similarity index 100%
rename from src/northbridge/via/vx900/romstrap.lds
rename to src/northbridge/via/vx900/romstrap.ld
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index db145d0..dacfc9c 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -20,4 +20,4 @@
 romstage-y += early_smbus.c
 
 chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
-chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds
+chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.ld
diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c
index b827dcf..1207a95 100644
--- a/src/southbridge/nvidia/ck804/nic.c
+++ b/src/southbridge/nvidia/ck804/nic.c
@@ -90,7 +90,7 @@
 	/* If that is invalid we will read that from romstrap. */
 	if (!eeprom_valid) {
 		u32 *mac_pos;
-		mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.lds. */
+		mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.ld. */
 		mac_l = read32(mac_pos) + nic_index;
 		mac_h = read32(mac_pos + 1);
 	}
diff --git a/src/southbridge/nvidia/ck804/romstrap.lds b/src/southbridge/nvidia/ck804/romstrap.ld
similarity index 100%
rename from src/southbridge/nvidia/ck804/romstrap.lds
rename to src/southbridge/nvidia/ck804/romstrap.ld
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index 03a34eb..b4dc460 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -19,4 +19,4 @@
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
 chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
-chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds
+chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.ld
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index 136d060..d8f691a 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -162,7 +162,7 @@
 //	if that is invalid we will read that from romstrap
 	if(!eeprom_valid) {
 		u32 *mac_pos;
-		mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.lds
+		mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.ld
 		mac_l = read32(mac_pos) + nic_index; // overflow?
 		mac_h = read32(mac_pos + 1);
 
diff --git a/src/southbridge/nvidia/mcp55/romstrap.lds b/src/southbridge/nvidia/mcp55/romstrap.ld
similarity index 100%
rename from src/southbridge/nvidia/mcp55/romstrap.lds
rename to src/southbridge/nvidia/mcp55/romstrap.ld
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index 1a9ea65..5c69622 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -14,4 +14,4 @@
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 
 chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
-chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds
+chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.ld
diff --git a/src/southbridge/sis/sis966/romstrap.lds b/src/southbridge/sis/sis966/romstrap.ld
similarity index 100%
rename from src/southbridge/sis/sis966/romstrap.lds
rename to src/southbridge/sis/sis966/romstrap.ld
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index 6d9407d..1c5ff3f 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -9,4 +9,4 @@
 ramstage-y += chrome.c
 
 chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
-chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds
+chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.ld
diff --git a/src/southbridge/via/k8t890/romstrap.lds b/src/southbridge/via/k8t890/romstrap.ld
similarity index 100%
rename from src/southbridge/via/k8t890/romstrap.lds
rename to src/southbridge/via/k8t890/romstrap.ld