Many Intel southbridges provide a mechanism called Back Up Control Top Swap (
BUC.TS). This functionality allows to have the southbridge fetch the reset vector or the beginning of the bootblock at a 64K/128/256K offset from the usual top of flash.
This can be useful in different ways:
The BUC.TS status is stored in a nvram bit. To clear it one has to remove the RTC battery.
First compile bucts by running make:
Then you can view the current system settings:
$ ./bucts --print
To flip the decode address of the bootblock, by setting
BUC.TS to 1:
$ ./bucts --set
To set the behavior the regular mapping, by setting
BUC.TS to 0
$ ./bucts --unset
Example Bootblock size of 64KB (this is only configurable to be something else like 128 or 256K on PCH Intel targets).