tree 8a62aa47481edf33b14659c821694319c893a35b
parent 542a2d908defd5a0aa01cda1e850cf37dcb7a1ca
author Lean Sheng Tan <lean.sheng.tan@intel.com> 1622041911 -0700
committer Werner Zeh <werner.zeh@siemens.com> 1622778343 +0000

soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset

Further add initial silicon UPD settings for:
- graphics & display
- chipset lockdown
- PAVP
- legacy timer
- PCH master gating control
- HECI

This CL also enables HECI 1 in devicetree.cb.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>