mediatek: Share watchdog timer code among similar SOCs

Refactor watchdog timer (WDT) code which will be reused among similar
SOCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: I745c2f204924d9eee1941c0f3e9b6ba45cfb1958
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27024
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/mediatek/mt8173/include/soc/wdt.h b/src/soc/mediatek/mt8173/include/soc/wdt.h
index 9ebed64..ddca102 100644
--- a/src/soc/mediatek/mt8173/include/soc/wdt.h
+++ b/src/soc/mediatek/mt8173/include/soc/wdt.h
@@ -13,12 +13,12 @@
  * GNU General Public License for more details.
  */
 
-#ifndef SOC_MEDIATEK_MT8173_WDT_H
-#define SOC_MEDIATEK_MT8173_WDT_H
+#ifndef SOC_MEDIATEK_COMMON_WDT_H
+#define SOC_MEDIATEK_COMMON_WDT_H
 
 #include <stdint.h>
 
-struct mt8173_wdt_regs {
+struct mtk_wdt_regs {
 	u32 wdt_mode;
 	u32 wdt_length;
 	u32 wdt_restart;
@@ -50,4 +50,4 @@
 
 int mtk_wdt_init(void);
 
-#endif /* SOC_MEDIATEK_MT8173_WDT_H */
+#endif /* SOC_MEDIATEK_COMMON_WDT_H */
diff --git a/src/soc/mediatek/mt8173/wdt.c b/src/soc/mediatek/mt8173/wdt.c
index 85fdbf5..bd2a614 100644
--- a/src/soc/mediatek/mt8173/wdt.c
+++ b/src/soc/mediatek/mt8173/wdt.c
@@ -20,14 +20,14 @@
 #include <soc/wdt.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
-static struct mt8173_wdt_regs *const mt8173_wdt = (void *)RGU_BASE;
+static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE;
 
 int mtk_wdt_init(void)
 {
 	uint32_t wdt_sta;
 
 	/* Write Mode register will clear status register */
-	wdt_sta = read32(&mt8173_wdt->wdt_status);
+	wdt_sta = read32(&mtk_wdt->wdt_status);
 
 	printk(BIOS_INFO, "WDT: Last reset was ");
 	if (wdt_sta & MTK_WDT_STA_HW_RST) {
@@ -49,7 +49,7 @@
 	 * ENABLE: disable watchdog on initialization.
 	 * Setting bit EXTEN to enable watchdog output.
 	 */
-	clrsetbits_le32(&mt8173_wdt->wdt_mode,
+	clrsetbits_le32(&mtk_wdt->wdt_mode,
 			MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
 			MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
 			MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
@@ -59,5 +59,5 @@
 
 void do_hard_reset(void)
 {
-	write32(&mt8173_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
+	write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
 }