southbridge/intel/bd82x6x: Use common gpio.c
Use shared gpio code from common folder.
Bd82x6x's gpio.c and gpio.h is used by other southbridges
as well and will be removed once it is unused.
Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13614
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
index 4bf6968..9ee32bb 100644
--- a/src/mainboard/samsung/lumpy/chromeos.c
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#define GPIO_SPI_WP 24
#define GPIO_REC_MODE 42
@@ -119,19 +120,16 @@
void init_bootmode_straps(void)
{
#ifdef __PRE_RAM__
- u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
- u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
- u32 gp_lvl = inl(gpio_base + GP_LVL);
u32 flags = 0;
/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */
- if (gp_lvl & (1 << GPIO_SPI_WP))
+ if (get_gpio(GPIO_SPI_WP))
flags |= (1 << FLAG_SPI_WP);
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
- if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32))))
+ if (!get_gpio(GPIO_REC_MODE))
flags |= (1 << FLAG_REC_MODE);
/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
- if (gp_lvl & (1 << GPIO_DEV_MODE))
+ if (get_gpio(GPIO_DEV_MODE))
flags |= (1 << FLAG_DEV_MODE);
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
diff --git a/src/mainboard/samsung/lumpy/gpio.c b/src/mainboard/samsung/lumpy/gpio.c
index e5737bb..8e8b936 100644
--- a/src/mainboard/samsung/lumpy/gpio.c
+++ b/src/mainboard/samsung/lumpy/gpio.c
@@ -16,7 +16,7 @@
#ifndef LUMPY_GPIO_H
#define LUMPY_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/common/gpio.h>
/*
* GPIO SET 1 includes GPIO0 to GPIO31
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 6425153..650c8d7 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -33,6 +33,7 @@
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index 8b6716a..5f2a062 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#define GPIO_SPI_WP 68
#define GPIO_REC_MODE 42
@@ -116,20 +117,16 @@
void init_bootmode_straps(void)
{
#ifdef __PRE_RAM__
- u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
- u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
- u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
- u32 gp_lvl = inl(gpio_base + GP_LVL);
u32 flags = 0;
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */
- if (gp_lvl3 & (1 << (GPIO_SPI_WP-64)))
+ if (get_gpio(GPIO_SPI_WP))
flags |= (1 << FLAG_SPI_WP);
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
- if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32))))
+ if (!get_gpio(GPIO_REC_MODE))
flags |= (1 << FLAG_REC_MODE);
/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
- if (gp_lvl & (1 << GPIO_DEV_MODE))
+ if (get_gpio(GPIO_DEV_MODE))
flags |= (1 << FLAG_DEV_MODE);
pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
diff --git a/src/mainboard/samsung/stumpy/gpio.c b/src/mainboard/samsung/stumpy/gpio.c
index 1371155..eb04c78 100644
--- a/src/mainboard/samsung/stumpy/gpio.c
+++ b/src/mainboard/samsung/stumpy/gpio.c
@@ -16,7 +16,7 @@
#ifndef STUMPY_GPIO_H
#define STUMPY_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/common/gpio.h>
/*
* GPIO SET 1 includes GPIO0 to GPIO31
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index ab1cb76..738f1ff 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -33,6 +33,7 @@
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>