commit e8e66f47631c505ab153d8a348058350b9acfe88
author Patrick Rudolph <siro@das-labor.org> Sat Feb 06 17:42:42 2016 +0100
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Thu Feb 18 01:35:57 2016 +0100
tree 535bc168855923222affbf6bdb06620cbd8fb343
parent ffc31d07f7839fa72073aae4ddbbd025ac4a7bac

southbridge/intel/bd82x6x: Use common gpio.c

Use shared gpio code from common folder.
Bd82x6x's gpio.c and gpio.h is used by other southbridges
as well and will be removed once it is unused.

Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13614
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/google/stout/chromeos.c

diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
index a2abaed..4c7a9f5 100644
--- a/src/mainboard/google/stout/chromeos.c
+++ b/src/mainboard/google/stout/chromeos.c
@@ -21,6 +21,7 @@
 #include <device/pci.h>
 
 #include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
 #include "ec.h"
 #include <ec/quanta/it8518/ec.h>
 
@@ -81,20 +82,7 @@
 
 int get_write_protect_state(void)
 {
-	device_t dev;
-#ifdef __PRE_RAM__
-	dev = PCI_DEV(0, 0x1f, 0);
-#else
-	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-#endif
-	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
-	if (!gpio_base)
-		return 0;
-
-	u32 gp_lvl = inl(gpio_base + GP_LVL);
-
-	return !((gp_lvl >> 7) & 1);
+	return !get_gpio(7);
 }
 
 int get_lid_switch(void)

src/mainboard/google/stout/gpio.c

diff --git a/src/mainboard/google/stout/gpio.c b/src/mainboard/google/stout/gpio.c
index 7fffe8b..43134ea 100644
--- a/src/mainboard/google/stout/gpio.c
+++ b/src/mainboard/google/stout/gpio.c
@@ -16,7 +16,7 @@
 #ifndef STOUT_GPIO_H
 #define STOUT_GPIO_H
 
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/common/gpio.h>
 
 const struct pch_gpio_set1 pch_gpio_set1_mode = {
 	.gpio0  = GPIO_MODE_GPIO,	/* GPIO0 */

src/mainboard/google/stout/romstage.c

diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 983988c..8348e4f 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -30,6 +30,7 @@
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>