tree 7b8294036e61fb45713214fb0cddcc671fa068fc
parent 53508fedf8bbd49b10f39a18b3bad6b25b71242e
author Duncan Laurie <dlaurie@chromium.org> 1342028445 -0700
committer Ronald G. Minnich <rminnich@gmail.com> 1352867897 +0100

Add ddr3lv_support flag to pei_data structure

This will enable DDR3 1.35V support for memory training in
the reference code.  It requires the board to be setup for
1.35V with whatever board-specific GPIOs are available.

Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1825
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>